Methods and Arrangements for Reverse Synchronization on a Wireless Medium

ABSTRACT

Logic to receive a first set of two or more timing management frames wherein one or more of the two or more timing management frames in the first set comprise a first adjusted follower clock value. Logic to calculate a second adjusted clock value. Logic to cause transmission of a second set of two or more timing management frames, wherein one or more of the two or more timing management frames in the second set comprise the second adjusted clock value. Logic to cause transmission of a first set of two or more acknowledgement frames. Logic to receive a second set of two or more acknowledgement frames. And logic to calculate a difference between the first adjusted follower clock value and the second adjusted clock value to determine a synchronization error, the synchronization error to represent a performance of the time synchronization.

TECHNICAL FIELD

This disclosure generally relates to systems and methods for wirelesscommunications and, more particularly, involve establishment of reversesynchronization on a wireless medium.

BACKGROUND

Synchronizing time across the components in a network is necessary for avariety of distributed, time-sensitive applications executing atdifferent nodes in the network. For synchronized time to be useful totime-sensitive applications, the synchronized time should meet criticalperformance requirements. Thus, networks offering time synchronizationfor time-sensitive applications requires the network to monitor the timesynchronization performance to ensure the synchronized time is accurateenough for a time-sensitive application's performance.

For wireless media, performance of time synchronization across thecomponents in a wireless network is more susceptible to channelconditions. So, monitoring the performance of time synchronization overthe wireless medium is critical.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1A depicts a system diagram illustrating an embodiment of a networkenvironment for synchronization logic circuitry, in accordance with oneor more example embodiments.

FIG. 1B depicts an embodiment illustrating interactions between stations(STAs) to establish multiple links between an access point (AP)multi-link device (MLD) and a non-AP MLD.

FIG. 1C depicts an embodiment of a system including multiple STAs toimplement synchronization logic circuitry, in accordance with one ormore example embodiments.

FIG. 1D illustrates an embodiment of a radio architecture for STAs, suchas the wireless interfaces for STAs depicted in FIGS. 1A-C, to implementsynchronization logic circuitry.

FIG. 1E illustrates an embodiment of front end module (FEM) circuitry ofa wireless interface for STAs, such as the STAs in FIGS. 1A-C, toimplement synchronization logic circuitry.

FIG. 1F illustrates an embodiment of radio integrated circuit (IC)circuitry of a wireless interface for STAs, such as the STAs in FIGS.1A-C, to implement synchronization logic circuitry.

FIG. 1G illustrates an embodiment of baseband processing circuitry of awireless interface for STAs, such as the STAs in FIGS. 1A-C, toimplement synchronization logic circuitry.

FIG. 2A depicts an embodiment of timing management frame.

FIG. 2B depicts an embodiment of a fine timing management frame.

FIG. 2C depicts an embodiment of a time synchronization timingmanagement session.

FIG. 2D depicts an embodiment of a time synchronization fine timingmanagement session.

FIG. 3 depicts an embodiment of service period access withsynchronization logic circuitry.

FIG. 4A depicts an embodiment of a flowchart to implementsynchronization logic circuitry.

FIG. 4B depicts another embodiment of a flowchart to implementsynchronization logic circuitry.

FIGS. 4C-D depict embodiments of flowcharts to generate and transmitframes and receive and interpret frames for communications betweenwireless communication devices.

FIG. 5 depicts an embodiment of a functional diagram of a wirelesscommunication device, in accordance with one or more example embodimentsof the present disclosure.

FIG. 6 depicts an embodiment of a block diagram of a machine upon whichany of one or more techniques may be performed, in accordance with oneor more embodiments.

FIGS. 7-8 depict embodiments of a computer-readable storage medium and acomputing platform to implement synchronization logic circuitry.

DETAILED DESCRIPTION OF EMBODIMENTS

The following description and the drawings sufficiently illustratespecific embodiments to enable those skilled in the art to practicethem. Other embodiments may incorporate structural, logical, electrical,process, algorithm, and other changes. Portions and features of someembodiments may be included in, or substituted for, those of otherembodiments. Embodiments set forth in the claims encompass all availableequivalents of those claims.

Embodiments may comprise synchronization logic circuitry to implementtime synchronization between a leader and a follower. The leader is adevice that is selected to maintain the time and followers adjust theirtimes to match the time of the leader. The following embodiments focusprimarily on the interactions between one follower and the leader butnote that, in many embodiments, each leader may have multiple followers.

Embodiments may determine performance information related to how closelya follower is time synched with a leader. For instance, the follower mayperform time-sensitive actions that may be coordinated with thetime-sensitive actions of one or more followers, other devices, events,and/or the like. Maintaining time synchronization of the followerswithin a maximum synchronization error is critical to the success of theapplications executing on the follower.

In many embodiments, the leader and the followers may comprise Wi-Fistations (STAs) that operate in accordance with one or more Institute ofElectrical and Electronics Engineers (IEEE) 802.11 standards such asIEEE 802.11-2020, December 2020. In such embodiments, the leader and thefollowers may also operate in accordance with a time-synchronizationstandard such as IEEE 802.1AS-2020.

In some embodiments, time synchronization is initiated as defined inIEEE 802.1AS-2020 Clause-12 using either the Timing Measurement™protocol or the Fine Timing Measurement (FTM) protocol. The FTM protocolmay offer a more accurate tuning of the times between he leader and thefollower such as timestamps within 10 nanoseconds.

With the execution of the TM or FTM protocol, the follower determinesthe relative offset of its local clock with respect to the clock at theleader. The estimated offset may oscillate for a while as the protocolproceeds. The oscillation may damp down around a value at which time thefollower may determine that it has reached a stable state.

The definition of ‘stable state’ is dependent on the set of applicationsthat require time synchronization and their requirements for timesynchronization performance. In general, the time synchronizationreaches the ‘stable state’ prior to the initiation of the applicationsthat require time synchronization and any perturbation from the ‘stablestate’ is actively monitored by the implementation using the reversesync and appropriate corrective actions are triggered to limit theperturbation(s) within an acceptable range.

Once the stable state is reached, many embodiments may initiate areverse sync. If the TM protocol is implemented, the follower starts bysending TM frames to the leader including a preciseOriginTimestamp fieldset to the adjusted follower clock (local clock at the follower+therelative offset of the local clock relative to that of the leader).

If the FTM protocol is implemented, the follower may send a FTM framewith a trigger field set to a value indicating that the stable state hasbeen achieved at the follower. The Leader waits for the Follower to sendan initial Fine Timing Measurement Request frame to start the next FTMsession The Leader in response sends an initial Fine Timing MeasurementRequest frame to the Follower; and then responds to the received initialFine Timing Measurement Request from the Follower with an initial FineTiming Measurement frame.

At the end of this exchange a FTM session for the Forward Sync isestablished; and FTM session for the Reverse Sync is established. FineTiming Measurement frames from the Follower to the Leader may include aframe where a preciseOriginTimestamp field is set to the adjustedfollower clock (local clock at the follower+the relative offset of thelocal clock relative to that of the leader).

If at the Follower, the estimated offset starts oscillating beyond thethresholds established for the stable state, the Reverse Sync operationis aborted; and will have to resume after the stable state is achieved.If the underlying 802.11 protocol is Timing Measurement protocol, theFollower simply stops sending Timing Measurement frames to the Leader.If the underlying 802.11 protocol is the Fine Timing Measurementprotocol, the Follower sends Fine Timing Measurement frame with just theTrigger field set to a value indicated that the Follower is not in thestable state anymore. The Leader in response will stop initialing FineTiming Measurement session negotiations for Reverse Sync.

Note that the Reverse Sync frames do not have to be transmitted duringevery TM session or FTM session. In many embodiments, some TM or FTMsessions may only include Forward Sync time synchronization. Forinstance, if the time synchronization error is low and has remained lowfor a predetermined time interval, some of the TM or FTM sessions maynot include Reverse Synchronization. In other embodiments, the reversesynchronization may occur each TM or FTM session. In some embodiments,the number of TM frames or FTM frames transmitted during a TM session orFTM session, respectively, may not be equal. For instance, the number offorward sync TM or FTM frames may be grater than the number of TM or FTMframes transmitted during the TM or FTM session.

In still other embodiments, the fine timing measurement protocol is usedfor Forward Sync and the timing measurement protocol is used for ReverseSync is possible. However, using the same protocol for both the ForwardSync and the Reverse Sync may be advantageous in relation to the natureof TM frame exchange being more regular versus the nature of FTM framesthat may require an initial FTM frame to initiate the FTM frameexchanges for Forward Sync or Reverse Sync.

In some embodiments, the Reverse Sync may also be used as a mechanism totrigger changing the parameters used for Forward Sync. For instance, ifthe estimated time synchronization error is far below what is requiredfor the supported time-sensitive applications, the parameters may betweaked to render the corresponding [Fine] Timing Measurement frameexchanges less frequent.

In some embodiments, links (or logical) communications channels may beestablished between multi-link devices (MLDs). MLDs include more thanone stations (STAs). For instance, an access point (AP) MLD and a non-APMLD may include STAs configured for frequency bands such as a first STAconfigured for 2.4 GHz communications, a second STA configured for 5 GHzcommunications, and a third STA configured for 6 GHz communications.

Note that STAs may be AP STAs or non-AP STAs and may each be associatedwith a specific link of an MLD. Note also that a MLD can include APfunctionality for one or more links and, if a STA of the MLD operates asan AP in a link, the STA is referred to as an AP STA. If the STA doesnot perform AP functionality, or does not operate as an AP, on a link,the STA is referred to as a non-AP STA. In many of the embodimentsherein, the AP MLDs operate as APs on active links, and the non-AP MLDsoperate as non-AP STAs on active links. However, an AP MLD may also haveSTAs that operate as non-AP STAs on the same extended service set (ESS)or basic service set (BSS) or other ESS's or BSS's.

For maintaining a quality of service (QoS), many embodiments define twoor more access categories. Access categories may be associated withtraffic to define priorities (in the form of parameter sets) for accessto a channel for transmissions (or communications traffic) such asmanaged link transmissions. Many embodiments implement an enhanceddistributed channel access (EDCA) protocol to establish the priorities.In some embodiments, the EDCA protocol includes access categories suchas best efforts (AC_BE), background (AC_BK), video (AC_VI), and voice(AC_VO). Protocols for various standards provide default values forparameter sets for each of the access categories and the values may varydepending upon the type of a STA, the operational role of the STA,and/or the like.

Embodiments may also comprise synchronization logic circuitry tofacilitate communications by stations (STAs) in accordance withdifferent versions of Institute of Electrical and Electronics Engineers(IEEE) 802.11 standards for wireless communications such as IEEE802.11-2020, December 2020; IEEE P802.11be™/D1.0, May 2021; IEEEP802.11ax™/D8.0, IEEE P802.11ay™/D7.0, IEEE P802.11az™/D3.0, IEEEP802.11ba™/D8.0, IEEE P802.11bb™/D0.4, IEEE P802.11bc™/D1.02, and IEEEP802.11bd™/D1.1.

The above descriptions are for purposes of illustration and are notmeant to be limiting. Numerous other examples, configurations,processes, algorithms, etc., may exist, some of which are described ingreater detail below. Example embodiments will now be described withreference to the accompanying figures.

Various embodiments may be designed to address different technicalproblems associated with time synchronization such as support fortime-sensitive applications; addressing time synchronization in awireless medium; monitor the time synchronization performance to ensurethe synchronized time is good enough in order to achieve thecorresponding application performance; monitoring the performance timesynchronization over the wireless medium; monitoring the performancetime synchronization over the wireless medium without significant costimpact for specialized hardware; and/or the like.

Different technical problems such as those discussed above may beaddressed by one or more different embodiments. Embodiments may addressone or more of these problems associated with time synchronization overa wireless medium. For instance, some embodiments that address problemsassociated with time synchronization over a wireless medium may do so byone or more different technical means, such as, receiving a first set oftwo or more timing management frames wherein one or more of the two ormore timing management frames in the first set comprise a first adjustedfollower clock value; causing transmission of a second set of two ormore timing management frames, wherein one or more of the two or moretiming management frames in the second set comprise a second adjustedclock value; transmitting a first set of two or more acknowledgementframes; receiving a second set of two or more acknowledgement frames;calculating the second adjusted clock value; calculating a differencebetween the first adjusted follower clock value and the second adjustedclock value to determine a synchronization error, the synchronizationerror to represent a performance of the time synchronization; causingtransmission of a first set of two or more timing management frameswherein one or more of the two or more timing management frames in thefirst set comprise a first adjusted leader clock value; receiving asecond set of two or more timing management frames, wherein one or moreof the two or more timing management frames in the second set comprise asecond adjusted clock value; receiving a first set of two or moreacknowledgement frames; calculating the second adjusted clock value;causing transmission of a second set of two or more acknowledgementframes; calculating a difference between the first adjusted leader clockvalue and the second adjusted clock value to determine a synchronizationerror, the synchronization error to represent a performance of the timesynchronization; and/or the like.

Several embodiments comprise central servers, access points (APs),and/or stations (STAs) such as modems, routers, switches, servers,workstations, netbooks, mobile devices (Laptop, Smart Phone, Tablet, andthe like), sensors, meters, controls, instruments, monitors, home oroffice appliances, Internet of Things (IoT) gear (watches, glasses,headphones, and the like), and the like. Some embodiments may provide,e.g., indoor and/or outdoor “smart” grid and sensor services. In variousembodiments, these devices relate to specific applications such ashealthcare, home, commercial office and retail, security, and industrialautomation and monitoring applications, as well as vehicle applications(automobiles, self-driving vehicles, airplanes, and the like), and thelike.

Some embodiments may facilitate wireless communications in accordancewith multiple standards. Some embodiments may comprise low powerwireless communications like Bluetooth®, cellular communications, andmessaging systems. Furthermore, some wireless embodiments mayincorporate a single antenna while other embodiments may employ multipleantennas or antenna elements.

While some of the specific embodiments described below will referencethe embodiments with specific configurations, those of skill in the artwill realize that embodiments of the present disclosure mayadvantageously be implemented with other configurations with similarissues or problems.

FIG. 1A depicts a system diagram illustrating an embodiment of a networkenvironment for synchronization logic circuitry, in accordance with oneor more example embodiments. Wireless network 1000 may include one ormore user devices 1020 and one or more access points(s) (AP) 1005, whichmay communicate in accordance with IEEE 802.11 communication standards.The user device(s) 1020 may comprise mobile devices that arenon-stationary (e.g., not having fixed locations) and/or stationarydevices.

In some embodiments, the user device(s) 1020 and the AP(s) 1005 mayinclude one or more computer systems similar to that of the functionaldiagram of FIG. 3 and/or the example machine/system of FIGS. 5, 6, 7,and 8.

One or more illustrative user device(s) 1020 and/or AP(s) 1005 may beoperable by one or more user(s) 1010. It should be noted that anyaddressable unit may be a station (STA). A STA may take on multipledistinct characteristics, each of which shape its function. For example,a single addressable unit might simultaneously be a portable STA, aquality-of-service (QoS) STA, a dependent STA, and a hidden STA. The oneor more illustrative user device(s) 1020 and the AP(s) 1005 may be STAs.The one or more illustrative user device(s) 1020 and/or AP(s) 1005 mayoperate as an extended service set (ESS), a basic service set (BSS), apersonal basic service set (PBSS), or a control point/access point(PCP/AP). The user device(s) 1020 (e.g., 1024, 1025, 1026, 1027, 1028,or 1029) and/or AP(s) 1005 may include any suitable processor-drivendevice including, but not limited to, a mobile device or a non-mobile,e.g., a static device. For example, user device(s) 1020 and/or AP(s)1005 may include, a user equipment (UE), a station (STA), an accesspoint (AP), a software enabled AP (SoftAP), a personal computer (PC), awearable wireless device (e.g., bracelet, watch, glasses, ring, etc.), adesktop computer, a mobile computer, a laptop computer, an Ultrabook™computer, a notebook computer, a tablet computer, a server computer, ahandheld computer, a handheld device, an internet of things (IoT)device, a sensor device, a PDA device, a handheld PDA device, anon-board device, an off-board device, a hybrid device (e.g., combiningcellular phone functionalities with PDA device functionalities), aconsumer device, a vehicular device, a non-vehicular device, a mobile orportable device, a non-mobile or non-portable device, a mobile phone, acellular telephone, a PCS device, a PDA device which incorporates awireless network interface, a mobile or portable GPS device, a DVBdevice, a relatively small computing device, a non-desktop computer, a“carry small live large” (CSLL) device, an ultra mobile device (UMD), anultra mobile PC (UMPC), a mobile internet device (MID), an “origami”device or computing device, a device that supports dynamicallycomposable computing (DCC), a context-aware device, a video device, anaudio device, an A/V device, a set-top-box (STB), a blu-ray disc (BD)player, a BD recorder, a digital video disc (DVD) player, a highdefinition (HD) DVD player, a DVD recorder, a HD DVD recorder, apersonal video recorder (PVR), a broadcast HD receiver, a video source,an audio source, a video sink, an audio sink, a stereo tuner, abroadcast radio receiver, a flat panel display, a personal media player(PMP), a digital video camera (DVC), a digital audio player, a speaker,an audio receiver, an audio amplifier, a gaming device, a data source, adata sink, a digital still camera (DSC), a media player, a smartphone, atelevision, a music player, or the like. Other devices, including smartdevices such as lamps, climate control, car components, householdcomponents, appliances, etc. may also be included in this list.

As used herein, the term “Internet of Things (IoT) device” is used torefer to any object (e.g., an appliance, a sensor, etc.) that has anaddressable interface (e.g., an Internet protocol (IP) address, aBluetooth identifier (ID), a near-field communication (NFC) ID, etc.)and can transmit information to one or more other devices over a wiredor wireless connection. An IoT device may have a passive communicationinterface, such as a quick response (QR) code, a radio-frequencyidentification (RFID) tag, an NFC tag, or the like, or an activecommunication interface, such as a modem, a transceiver, atransmitter-receiver, or the like. An IoT device can have a particularset of attributes (e.g., a device state or status, such as whether theIoT device is on or off, open or closed, idle or active, available fortask execution or busy, and so on, a cooling or heating function, anenvironmental monitoring or recording function, a light-emittingfunction, a sound-emitting function, etc.) that can be embedded inand/or controlled/monitored by a central processing unit (CPU),microprocessor, ASIC, or the like, and configured for connection to anIoT network such as a local ad-hoc network or the Internet. For example,IoT devices may include, but are not limited to, refrigerators,toasters, ovens, microwaves, freezers, dishwashers, dishes, hand tools,clothes washers, clothes dryers, furnaces, air conditioners,thermostats, televisions, light fixtures, vacuum cleaners, sprinklers,electricity meters, gas meters, etc., so long as the devices areequipped with an addressable communications interface for communicatingwith the IoT network. IoT devices may also include cell phones, desktopcomputers, laptop computers, tablet computers, personal digitalassistants (PDAs), etc. Accordingly, the IoT network may be comprised ofa combination of “legacy” Internet-accessible devices (e.g., laptop ordesktop computers, cell phones, etc.) in addition to devices that do nottypically have Internet-connectivity (e.g., dishwashers, etc.).

In some embodiments, the user device(s) 1020 and/or AP(s) 1005 may alsoinclude mesh stations in, for example, a mesh network, in accordancewith one or more IEEE 802.11 standards and/or 3GPP standards.

Any of the user device(s) 1020 (e.g., user devices 1024, 1025, 1026,1027, 1028, and 1029) and AP(s) 1005 may be configured to communicatewith each other via one or more communications networks 1030 and/or 1035wirelessly or wired. In some embodiments, the user device(s) 1020 mayalso communicate peer-to-peer or directly with each other with orwithout the AP(s) 1005 and, in some embodiments, the user device(s) 1020may also communicate peer-to-peer if enabled by the AP(s) 1005.

Furthermore, the AP(s) 1005 may comprise more than one AP MLDs eachcomprising synchronization logic circuitry to implement timesynchronization. For instance, some applications may require one or moreSTAs maintain closely synchronized clocks for coordination betweenmultiple devices, STAs, and the like. Such applications are oftenreferred to as time-sensitive applications and may have specificationsrelated to performance such as the maintenance of a synchronizationerror below some maximum synchronization error such as 20 nanoseconds.While time-sensitive applications have historically operated onproprietary systems and have recently implement some hardwired,standardized network components, wireless embodiments such as AP(s) 1005and user device 1020 with synchronization logic circuitry may offeradvantages of not only the time synchronization performance andmonitoring but also wireless communications between the STAs, devices,and the like, operating in a time-sensitive network (TSN).

In the present embodiment, the AP(s) 1005 may be selected to be a leaderin relation to maintaining an accurate clock and one or more of the userdevices 1022 may be followers such as the user device 1027. The userdevice 1027 may execute one or more time-sensitive applications thathave specific performance requirements for time synchronization betweenthe user device 1027 and the AP(s) 1005.

The synchronization logic circuitry of the user device 1027 mayperiodically initiate timing management TM sessions that involvedetermining a synchronization error to quantify a performance of thetime synchronization between the AP(s) 1005 and the user device 1027. Inmany embodiments, the TM sessions may involve interlacing burst offorward sync TM frame and reverse sync TM frames. For instance, thefollower may start the TM session by transmitting a TM frame (R1) forreverse sync at time t_(R)1 and capturing the time t1. The AP(s) 1005may receive the TM frame (R1) for reverse sync a time t_(R)2.Thereafter, at time t_(F)1, the leader may transit a TM frame (F1) forforward sync and an acknowledgement (ACK) (R1) at time t_(R)3 inresponse to the TM frame (R1). The ACK (R1) may include the time ofarrival of the TM frame (R1) at the AP(s) 1005, time t_(R)2, as well asthe time of departure of the ACK (R1), time t_(R)3 to provide thefollower, user device 1027, with information needed to calculate anoffset between the AP(s) 1005 (leader) clock and the clock of the userdevice 1027 (follower).

The user device 1027 may receive the TM frame (F1) at time t_(F)2, andmay transmit a TM frame (R2) at time t¹ _(R)1. The TM frame (R2) mayinclude a calculation of the offset between the AP(s) 1005 (leader)clock and the clock of the user device 1027 (follower) in a field of theTM frame (R2) and/or the TM frame (R2) may include a calculation of thelocal clock of the follower plus the offset between the AP(s) 1005(leader) clock and the clock of the user device 1027 (follower) in afield of the TM frame (R2). Similarly, after receipt of an ACK (F1), theAP(s) 1005 may calculate the offset between the clock of the AP(s) 1005and/or the sum of the offset and the local clock of the leader, AP(s)1005.

The frame exchanges may continue to exchange, e.g., three or more TMframes for forward sync and, e.g., 3 or more TM frames for reverse sync,calculating the offsets between the clocks and/or the local clock timesplus or minus the offsets to determine the estimated follower's clockand/or the estimated leader's clock. In some embodiments, the follower,user device 1027, may calculate the difference between a first adjustedtime calculated by the leader, which is received via a TM frame, and asecond adjusted time calculated by the follower to determine asynchronization error. In other words, the AP(s) 1005 can calculate thedelay caused by transmission of the TM frames and ACKs as a clock offsetat the receiving STA relative to the sending STA as equal to[(t2−t1)−(t4−t3)]/2. If the offsets differ, the difference is asynchronization error and the follower, user device 1027, may takemitigating measures to address the performance issues and/or accept thesynchronization error as representative of the performance of the timesynchronization via the synchronization logic circuitry of the followerand the leader.

In other embodiments, the forward sync and the reverse sync TM frametransmissions do not have to be interleaved. For instance, four forwardsync TM frames may be transmitted and four ACKs received in responseprior to transmitting the reverse sync frames and ACKs, or vice versa.In still other embodiments, the forward sync and the reverse sync TMframe transmissions may be interleaved differently. For instance, thesynchronization logic circuitry may transmit a forward sync TM frame andreceive an ACK prior to receipt of a reverse sync TM frame andtransmission of an ACK in response.

Any of the communications networks 1030 and/or 1035 may include, but notlimited to, any one of a combination of different types of suitablecommunications networks such as, for example, broadcasting networks,cable networks, public networks (e.g., the Internet), private networks,wireless networks, cellular networks, or any other suitable privateand/or public networks. Further, any of the communications networks 1030and/or 1035 may have any suitable communication range associatedtherewith and may include, for example, global networks (e.g., theInternet), metropolitan area networks (MANs), wide area networks (WANs),local area networks (LANs), or personal area networks (PANs). Inaddition, any of the communications networks 1030 and/or 1035 mayinclude any type of medium over which network traffic may be carriedincluding, but not limited to, coaxial cable, twisted-pair wire, opticalfiber, a hybrid fiber coaxial (HFC) medium, microwave terrestrialtransceivers, radio frequency communication mediums, white spacecommunication mediums, ultra-high frequency communication mediums,satellite communication mediums, or any combination thereof.

Any of the user device(s) 1020 (e.g., user devices 1024, 1025, 1026,1027, 1028, and 1029) and AP(s) 1005 may include one or morecommunications antennas. The one or more communications antennas may beany suitable type of antennas corresponding to the communicationsprotocols used by the user device(s) 1020 (e.g., user devices 1024,1025, 1026, 1027, 1028, and 1029) and AP(s) 1005. Some non-limitingexamples of suitable communications antennas include Wi-Fi antennas,Institute of Electrical and Electronics Engineers (IEEE) 802.11 familyof standards compatible antennas, directional antennas, non-directionalantennas, dipole antennas, folded dipole antennas, patch antennas,multiple-input multiple-output (MIMO) antennas, omnidirectionalantennas, quasi-omnidirectional antennas, or the like. The one or morecommunications antennas may be communicatively coupled to a radiocomponent to transmit and/or receive signals, such as communicationssignals to and/or from the user devices 1020 and/or AP(s) 1005.

Any of the user device(s) 1020 (e.g., user devices 1024, 1025, 1026,1027, 1028, and 1029) and AP(s) 1005 may be configured to wirelesslycommunicate in a wireless network. Any of the user device(s) 1020 (e.g.,user devices 1024, 1025, 1026, 1027, 1028, and 1029) and AP(s) 1005 maybe configured to perform such directional transmission and/or receptionusing a set of multiple antenna arrays (e.g., DMG antenna arrays or thelike). Each of the multiple antenna arrays may be used for transmissionand/or reception in a particular respective direction or range ofdirections. Any of the user device(s) 1020 (e.g., user devices 1024,1025, 1026, 1027, 1028, and 1029) and AP(s) 1005 may be configured toperform any given directional transmission towards one or more definedtransmit sectors. Any of the user device(s) 1020 (e.g., user devices1024, 1025, 1026, 1027, 1028, and 1029) and AP(s) 1005 may be configuredto perform any given directional reception from one or more definedreceive sectors.

MIMO beamforming in a wireless network may be accomplished using RFbeamforming and/or digital beamforming. In some embodiments, inperforming a given MIMO transmission, user devices 1020 and/or AP(s)1005 may be configured to use all or a subset of its one or morecommunications antennas to perform MIMO beamforming.

Any of the user devices 1020 (e.g., user devices 1024, 1025, 1026, 1027,1028, and 1029) and AP(s) 1005 may include any suitable radio and/ortransceiver for transmitting and/or receiving radio frequency (RF)signals in the bandwidth and/or channels corresponding to thecommunications protocols utilized by any of the user device(s) 1020 andAP(s) 1005 to communicate with each other. The radio components mayinclude hardware and/or software to modulate and/or demodulatecommunications signals according to pre-established transmissionprotocols. The radio components may further have hardware and/orsoftware instructions to communicate via one or more Wi-Fi and/or Wi-Fidirect protocols, as standardized by the Institute of Electrical andElectronics Engineers (IEEE) 802.11 standards. In certain exampleembodiments, the radio component, in cooperation with the communicationsantennas, may be configured to communicate via 2.4 GHz channels (e.g.,802.11b, 802.11g, 802.11n, 802.11ax, 802.11be), 5 GHz channels (e.g.,802.11n, 802.11ac, 802.11ax, 802.11be), 6 GHz (e.g., 802.11be), or 60GHz channels (e.g., 802.11ad, 802.11ay, Next Generation Wi-Fi) or 800MHz channels (e.g., 802.11ah). The communications antennas may operateat 28 GHz, 40 GHz, or any carrier frequency between 45 GHz and 75 GHz.It should be understood that this list of communication channels inaccordance with certain 802.11 standards is only a partial list, andthat other 802.11 standards may be used (e.g., Next Generation Wi-Fi, orother standards). In some embodiments, non-Wi-Fi protocols may be usedfor communications between devices, such as Bluetooth, dedicatedshort-range communication (DSRC), Ultra-High Frequency (UHF) (e.g., IEEE802.11af, IEEE 802.22), white band frequency (e.g., white spaces), orother packetized radio communications. The radio component may includeany known receiver and baseband suitable for communicating via thecommunications protocols. The radio component may further include apower amplifier (PA), a low noise amplifier (LNA), additional signalamplifiers, an analog-to-digital (A/D) converter, one or more buffers,and a digital baseband.

FIG. 1B depicts an embodiment 1100 illustrating interactions betweenstations (STAs) to establish multiple links between an access point (AP)multi-link device (MLD) 1120 and a non-AP MLD 1130. The AP MLD 1120 hasthree affiliated AP STAs: AP STA 1 operates on 2.4 GHz band, AP STA 2operates on 5 GHz band, and AP STA 3 operates on 6 GHz band. The non-APSTA 1 affiliated with the non-AP MLD 1130 sends an association requestframe (or a reassociation request frame) to AP STA 1 affiliated with theAP MLD 1120. The association request frame may have a TA field set tothe MAC address of the non-AP STA 1 and an RA field set to the MACaddress of the AP STA 1. The association request frame may includecomplete information of non-AP STA 1, non-AP STA 2, and non-AP STA 3 torequest up to four links to be setup (one link between AP STA 1 andnon-AP STA 1, one link between AP STA 2 and non-AP STA 2, and one linkbetween AP STA 3 and non-AP STA 3) and a multi-link (ML) element thatindicates the MLD MAC address of the non-AP MLD 1130.

AP STA 1, affiliated with the AP MLD 1120, may send an associationresponse frame to non-AP STA 1 affiliated with the non-AP MLD 1130 witha TA field of the association response frame is set to the MAC addressof the AP STA 1 and an RA field of the association response frame set tothe MAC address of the non-AP STA 1, to indicate successful multi-linksetup 1140. The association response frame may include completeinformation of AP STA 1, AP STA 2, and AP STA 3 and an ML element thatindicates the MLD MAC address of the AP MLD 1120. After successful MLsetup between the non-AP MLD 1130 and the AP MLD 1120, three links aresetup (LINK 1 between AP 1 and non-AP STA 1, LINK 2 between AP 2 andnon-AP STA 2, and LINK 3 between AP STA 3 and non-AP STA 3).

In some embodiments, the non-AP MLD 1130 may associate with less thanall the links available from the AP MLD 1120 for various reasons. Forinstance, in some embodiments, the non-AP MLD 1130 may only be capableof establishing two of the links. In some embodiments, the non-AP MLD1130 may establish a link with a second AP MLD because the second AP MLDmay have a better signal-to-noise ratio associated with one or morelinks and be associated with the same ESS. In some embodiments, thenon-AP MLD 1130 may establish a link with a second AP MLD because thesecond AP MLD may be associated with a different ESS or a BSS that isnot associated with the BSS of the AP MLD 1120.

During the association process, the AP MLD 1120 may establishcommunications protocols including identification of any parameters thatdiffer from default parameters, preferential communications protocols,and/or negotiate communications protocols for the links.

FIG. 1C depicts an embodiment of a system 1200 including multiple MLDSTAs to implement synchronization logic circuitry, in accordance withone or more example embodiments. System 1200 may transmit or receive aswell as generate, decode, and interpret transmissions between an AP MLD1210 and multiple MLD STAs 1230, 1290, 1292, 1294, 1296, and 1298,associated with the AP MLD 1210. The AP MLD 1210 may be wired andwirelessly connected to each of the MLD STAs 1230, 1290, 1292, 1294,1296, and 1298.

In some embodiments, the AP MLD 1210 and MLD STA 1230 may include one ormore computer systems similar to that of the example machines/systems ofFIGS. 5, 6, 7, and 8.

Each MLD STA 1230, 1290, 1292, 1294, 1296, and 1298 may includesynchronization logic circuitry, such as the synchronization logiccircuitry 1250 of MLD STA 1230, to associate with the AP MLD 1210 tosynchronize the clock (TSF timer 1205) with the clocks (e.g., TSF timer1235) of the MLD STAs 1230, 1290, 1292, 1294, 1296, and 1298. Forexample, the AP MLD 1210 may be selected as the leader and the MLD STAs1230, 1290, 1292, 1294, 1296, and 1298 may be followers.

After associating with the AP MLD 1210, one or more of the MLD STAs1230, 1290, 1292, 1294, 1296, and 1298 may initiate time synchronizationwith the AP MLD 1210. Time synchronization may involve a TM session oran FTM session. The TM session may include the transmission of TM framesfrom the follower (e.g., MLD STA 1230) to the leader (e.g., AP MLD 1210)as well as transmission of TM frames from the leader (e.g., AP MLD 1210)to the follower (e.g., MLD STA 1230). Transmission of TM frames from thefollower to the leader is defined as reverse synchronization (reversesync) and the transmission of TM frames from the leader to the followeris defined as forward synchronization (forward sync).

During forward sync, the synchronization logic circuitry 1220 of the APMLD 1210 may transmit a set of two or more TM frames or FTM frames tothe MLD STA 1230 and the synchronization logic circuitry 1250 of the MLDSTA 1230 may respond with an ACK that carries the arrival time (t_(F)2)of the first TM frame and the transmission (or departure) time (t_(F)3)of the first ACK. When the AP MLD 1210 transmits the second TM frame,the AP MLD 1210 may include the transmission time (t_(F)1) of the firstTM frame and the arrival time (t_(F)4) of the first ACK in the second TMframe. At the arrival of the second TM frame at the MLD STA 1230, thesynchronization logic circuitry 1250 of the MLD STA 1230 may havet_(F)1, t_(F)2, t_(F)3, and t_(F)4 as well as the timestamp of the TMframe. The synchronization logic circuitry 1230 of the MLD STA 1230 maycalculate the offset of the local clock relative to the clock of the APMLD 1210 as [(t_(F)2−t_(F)1)−(t_(F)4−t_(F)3)]/2.

During reverse sync, the synchronization logic circuitry 1250 of the MLDSTA 1230 may transmit a set of two or more TM frames or FTM frames tothe AP MLD 1210 and the synchronization logic circuitry 1220 of the APMLD 1210 may respond with an ACK that carries the arrival time (t_(R)2)of the first TM frame and the transmission (or departure) time (t_(R)3)of the first ACK. When the MLD STA 1230 transmits the second TM frame,the MLD STA 1213 may include the transmission time (t_(R)1) of the firstTM frame and the arrival time (t_(R)4) of the first ACK in the second TMframe. At the arrival of the second TM frame at the AP MLD 1210, thesynchronization logic circuitry 1220 of the AP MLD 1210 may have t_(R)1,t_(R)2, t_(R)3, and t_(R)4 as well as the timestamp of the TM frame. Thesynchronization logic circuitry 1220 of the AP MLD 1210 may calculatethe offset of the local clock relative to the clock of the MLD STA 1230as [(t_(R)2−t_(R)1)−(t_(R)4−t_(R)3)]/2.

Furthermore, the synchronization logic circuitry 1250 of the MLD STA1230 may include in the second TM frame of the reverse sync, apreciseOriginTimestamp field set to the adjusted follower clock (localclock at the follower+the relative offset of the local clock relative tothat of the leader). The synchronization logic circuitry 1220 of the APMLD STA 1210 may include in the second TM frame of the forward sync, apreciseOriginTimestamp field set to the adjusted leader clock (localclock at the leader+the relative offset of the local clock relative tothat of the follower).

The synchronization logic circuitry 1250 of the MLD STA 1230 maycalculate a difference between the adjusted follower clock value and theadjusted leader clock value to determine a synchronization error, thesynchronization error to represent a performance of the timesynchronization. Monitoring of the synchronization error is important toguaranteeing a time synchronization for time sensitive applications. Forinstance, when the forward sync is executed, the follower computes a‘forward sync’ offset which when added to the follower's clock shouldrender the follower's clock to be synchronized to that of the leader. Ifthere are no synchronization errors, the leader's clock and thefollower's clock plus ‘forward sync’ offset should be exactly same (andthe synchronization error therefore would be zero).

When executing the reverse sync, the follower sends the computed‘forward sync’ offset to the leader. The leader computes a ‘reversesync’ offset as a result of executing the reverse sync protocol with thefollower. One might expect the error in synchronization to be the samein both directions (even with Wi-Fi multipath conditions as timestampsare derived from the transmission of ‘FTM frames and the receipt ofcorresponding ACKs). The difference between the ‘reverse sync’ offsetand the ‘forward sync’ offset may provide the lower bound of how bestthe two implementations can be synchronized.

In some embodiments, the MLD STAs 1230, 1290, 1292, 1294, 1296, and 1298may individually negotiate time synchronization links and channelswithin the links that may be available for time synchronization. Infurther embodiments, the AP MLD 1210 may have a predetermined, default,or preferred set of links and channels that may be used for timesynchronization. In some embodiments, parameters related to timesynchronization may be negotiated by inclusion of parameters in aninitial FTM frame that a follower may send to the AP MLD 1210 toinitiate time synchronization. If the AP MLD 1210 accepts the parametersin the initial FTM frame from the follower, the AP MLD 1210 may proceedwith an FTM session in response to the initial FTM frame. On the otherhand, if the AP MLD 1210 does not accept the parameters in the initialFTM frame, the FTM session may end after transmission of the initial FTMframe from the follower.

In some embodiments, the synchronization logic circuitry 1220 of the APMLD 1210 may negotiate a bandwidth of an FTM session with thesynchronization logic circuitry 1250 of the MLD STA 1230. In someembodiments, the accuracy of time synchronization through forward syncand reverse sync may improve with wider bandwidths such as 20 MHz, 40MHz, 80 MHz, 160 MHz, and/or the like. For instance, timesynchronization on a 40 MHz bandwidth may be more accurate than timesynchronization on a 20 MHz bandwidth.

The AP MLD 1210 and MLD STA 1230 may comprise processor(s) 1201 andmemory 1231, respectively. The processor(s) 1201 may comprise any dataprocessing device such as a microprocessor, a microcontroller, a statemachine, and/or the like, and may execute instructions or code in thememory 1211. The memory 1211 may comprise a storage medium such asDynamic Random Access Memory (DRAM), read only memory (ROM), buffers,registers, cache, flash memory, hard disk drives, solid-state drives, orthe like. The memory 1211 may store 1212 the frames, frame structures,frame headers, etc., and may also comprise code to generate, scramble,encode, decode, parse, and interpret MAC frames and/or PHY frames andPPDUs.

The baseband processing circuitry 1218 may comprise a baseband processorand/or one or more circuits to implement an MLD management entity and astation management entity per link. The MLD management entity maycoordinate management of, communications between, and interactionsbetween station management entities for the links.

In some embodiments, the station management entity may interact with aMAC layer management entity to perform MAC layer functionality and a PHYmanagement entity to perform PHY functionality. In such embodiments, thebaseband processing circuitry 1218 may interact with processor(s) 1201to coordinate higher layer functionality with MAC layer and PHYfunctionality.

In some embodiments, the baseband processing circuitry 1218 may interactwith one or more analog devices to perform PHY functionality such asscrambling, encoding, modulating, and the like. In other embodiments,the baseband processing circuitry 1218 may execute code to perform oneor more of the PHY functionality such as scrambling, encoding,modulating, and the like.

The MAC layer functionality may execute MAC layer code stored in thememory 1211. In further embodiments, the MAC layer functionality mayinterface the processor(s) 1201.

The MAC layer functionality may communicate with the PHY to transmit aMAC frame such as a multiple-user (MU) ready to send (RTS), referred toas a MU-RTS, in a PHY frame such as an extremely high throughput (EHT)MU PPDU to the MLD STA 1230. The MAC layer functionality may generateframes such as management, data, and control frames.

The PHY may prepare the MAC frame for transmission by, e.g., determininga preamble to prepend to a MAC frame to create a PHY frame. The preamblemay include one or more short training field (STF) values, long trainingfield (LTF) values, and signal (SIG) field values. A wireless networkinterface 1222 or the baseband processing circuitry 1218 may prepare thePHY frame as a scrambled, encoded, modulated PPDU in the time domainsignals for the radio 1224. Furthermore, the TSF timer 1205 may providea timestamp value to indicate the time at which the PPDU is transmitted.

After processing the PHY frame, a radio 1224 may impress digital dataonto subcarriers of RF frequencies for transmission. The front endmodule may include one or more stages of filtering and one or morestages of amplification including at least one power amplifier (PA) toprepare the subcarriers of RF frequencies for transmission byelectromagnetic radiation via elements of an antenna array or antennas1224 and via the network 1280 to a receiving MLD STA such as the MLD STA1230.

The wireless network I/F 1222 also comprises a receiver. The receiverreceives electromagnetic energy, extracts the digital data, and theanalog PHY and/or the baseband processor 1218 decodes a PHY frame and aMAC frame from a PPDU.

The MLD STA 1230 may receive the MU-RTS in the EHT MU PPDU from the APMLD 1210 via the network 1280. The MLD STA 1230 may compriseprocessor(s) 1231 and memory 1241. The processor(s) 1231 may compriseany data processing device such as a microprocessor, a microcontroller,a state machine, and/or the like, and may execute instructions or codein the memory 1241. The memory 1241 may comprise a storage medium suchas Dynamic Random Access Memory (DRAM), read only memory (ROM), buffers,registers, cache, flash memory, hard disk drives, solid-state drives, orthe like. The memory 1241 may store 1242 the frames, frame structures,frame headers, etc., and may also comprise code to generate, scramble,encode, decode, parse, and interpret MAC frames and/or PHY frames(PPDUs).

The baseband processing circuitry 1248 may comprise a baseband processorand/or one or more circuits to implement a station management entity andthe station management entity may interact with a MAC layer managemententity to perform MAC layer functionality and a PHY management entity toperform PHY functionality. In such embodiments, the baseband processingcircuitry 1248 may interact with processor(s) 1231 to coordinate higherlayer functionality with MAC layer and PHY functionality.

In some embodiments, the baseband processing circuitry 1218 may interactwith one or more analog devices to perform PHY functionality such asdescrambling, decoding, demodulating, and the like. In otherembodiments, the baseband processing circuitry 1218 may execute code toperform one or more of the PHY functionalities such as descrambling,decoding, demodulating, and the like.

The MLD STA 1230 may receive the EHT MU PPDU at the antennas 1258, whichpass the signals along to the FEM 1256. The FEM 1256 may comprise one ormore stages of filtering and amplification including at least one lownoise amplifier (LNA) and may pass the signals to the radio 1254. Theradio 1254 may filter the carrier signals from the signals and determineif the signals represent a PPDU. If so, analog circuitry of the wirelessnetwork I/F 1252 or physical layer functionality implemented in thebaseband processing circuitry 1248 may demodulate, decode, descramble,etc. the PPDU. The baseband processing circuitry 1248 may identify,parse, and interpret the MAC MU-RTS from the physical layer service dataunit (PSDU) of the EHT MU PPDU.

FIG. 1D is a block diagram of a radio architecture 1300 such as thewireless communications I/F 1222 and 1252 in accordance with someembodiments that may be implemented in, e.g., the AP MLD 1210 and/or theMLD STA 1230 of FIG. 1C. The radio architecture 1300 may include radiofront-end module (FEM) circuitry 1304 a-b, radio IC circuitry 1306 a-band baseband processing circuitry 1308 a-b. The radio architecture 1300as shown includes both Wireless Local Area Network (WLAN) functionalityand Bluetooth (BT) functionality although embodiments are not solimited. In this disclosure, “WLAN” and “Wi-Fi” are usedinterchangeably.

FEM circuitry 1304 a-b may include a WLAN or Wi-Fi FEM circuitry 1304 aand a Bluetooth (BT) FEM circuitry 1304 b. The WLAN FEM circuitry 1304 amay include a receive signal path comprising circuitry configured tooperate on WLAN RF signals received from one or more antennas 1301, toamplify the received signals and to provide the amplified versions ofthe received signals to the WLAN radio IC circuitry 1306 a for furtherprocessing. The BT FEM circuitry 1304 b may include a receive signalpath which may include circuitry configured to operate on BT RF signalsreceived from one or more antennas 1301, to amplify the received signalsand to provide the amplified versions of the received signals to the BTradio IC circuitry 1306 b for further processing. FEM circuitry 1304 amay also include a transmit signal path which may include circuitryconfigured to amplify WLAN signals provided by the radio IC circuitry1306 a for wireless transmission by one or more of the antennas 1301. Inaddition, FEM circuitry 1304 b may also include a transmit signal pathwhich may include circuitry configured to amplify BT signals provided bythe radio IC circuitry 1306 b for wireless transmission by the one ormore antennas. In the embodiment of FIG. 1D, although FEM 1304 a and FEM1304 b are shown as being distinct from one another, embodiments are notso limited, and include within their scope the use of an FEM (not shown)that includes a transmit path and/or a receive path for both WLAN and BTsignals, or the use of one or more FEM circuitries where at least someof the FEM circuitries share transmit and/or receive signal paths forboth WLAN and BT signals.

Radio IC circuitry 1306 a-b as shown may include WLAN radio IC circuitry1306 a and BT radio IC circuitry 1306 b. The WLAN radio IC circuitry1306 a may include a receive signal path which may include circuitry todown-convert WLAN RF signals received from the FEM circuitry 1304 a andprovide baseband signals to WLAN baseband processing circuitry 1308 a.BT radio IC circuitry 1306 b may in turn include a receive signal pathwhich may include circuitry to down-convert BT RF signals received fromthe FEM circuitry 1304 b and provide baseband signals to BT basebandprocessing circuitry 1308 b. WLAN radio IC circuitry 1306 a may alsoinclude a transmit signal path which may include circuitry to up-convertWLAN baseband signals provided by the WLAN baseband processing circuitry1308 a and provide WLAN RF output signals to the FEM circuitry 1304 afor subsequent wireless transmission by the one or more antennas 1301.BT radio IC circuitry 1306 b may also include a transmit signal pathwhich may include circuitry to up-convert BT baseband signals providedby the BT baseband processing circuitry 1308 b and provide BT RF outputsignals to the FEM circuitry 1304 b for subsequent wireless transmissionby the one or more antennas 1301. In the embodiment of FIG. 1D, althoughradio IC circuitries 1306 a and 1306 b are shown as being distinct fromone another, embodiments are not so limited, and include within theirscope the use of a radio IC circuitry (not shown) that includes atransmit signal path and/or a receive signal path for both WLAN and BTsignals, or the use of one or more radio IC circuitries where at leastsome of the radio IC circuitries share transmit and/or receive signalpaths for both WLAN and BT signals.

Baseband processing circuitry 1308 a-b may include a WLAN basebandprocessing circuitry 1308 a and a BT baseband processing circuitry 1308b. The WLAN baseband processing circuitry 1308 a may include a memory,such as, for example, a set of RAM arrays in a Fast Fourier Transform orInverse Fast Fourier Transform block (not shown) of the WLAN basebandprocessing circuitry 1308 a. Each of the WLAN baseband circuitry 1308 aand the BT baseband circuitry 1308 b may further include one or moreprocessors and control logic to process the signals received from thecorresponding WLAN or BT receive signal path of the radio IC circuitry1306 a-b, and to also generate corresponding WLAN or BT baseband signalsfor the transmit signal path of the radio IC circuitry 1306 a-b. Each ofthe baseband processing circuitries 1308 a and 1308 b may furtherinclude physical layer (PHY) and medium access control layer (MAC)circuitry, and may further interface with a device for generation andprocessing of the baseband signals and for controlling operations of theradio IC circuitry 1306 a-b.

Referring still to FIG. 1D, according to the shown embodiment, WLAN-BTcoexistence circuitry 1313 may include logic providing an interfacebetween the WLAN baseband circuitry 1308 a and the BT baseband circuitry1308 b to enable use cases requiring WLAN and BT coexistence. Inaddition, a switch circuitry 1303 may be provided between the WLAN FEMcircuitry 1304 a and the BT FEM circuitry 1304 b to allow switchingbetween the WLAN and BT radios according to application needs. Inaddition, although the antennas 1301 are depicted as being respectivelyconnected to the WLAN FEM circuitry 1304 a and the BT FEM circuitry 1304b, embodiments include within their scope the sharing of one or moreantennas as between the WLAN and BT FEMs, or the provision of more thanone antenna connected to each of FEM 1304 a or 1304 b.

In some embodiments, the front-end module circuitry 1304 a-b, the radioIC circuitry 1306 a-b, and baseband processing circuitry 1308 a-b may beprovided on a single radio card, such as wireless network interface card(NIC) 1302. In some other embodiments, the one or more antennas 1301,the FEM circuitry 1304 a-b and the radio IC circuitry 1306 a-b may beprovided on a single radio card. In some other embodiments, the radio ICcircuitry 1306 a-b and the baseband processing circuitry 1308 a-b may beprovided on a single chip or integrated circuit (IC), such as IC 1312.

In some embodiments, the wireless NIC 1302 may include a WLAN radio cardand may be configured for Wi-Fi communications, although the scope ofthe embodiments is not limited in this respect. In some of theseembodiments, the radio architecture 1300 may be configured to receiveand transmit orthogonal frequency division multiplexed (OFDM) ororthogonal frequency division multiple access (OFDMA) communicationsignals over a multicarrier communication channel. The OFDM or OFDMAsignals may comprise a plurality of orthogonal subcarriers.

In some of these multicarrier embodiments, radio architecture 1300 maybe part of a Wi-Fi communication station (STA) such as a wireless accesspoint (AP), a base station or a mobile device including a Wi-Fi device.In some of these embodiments, radio architecture 1300 may be configuredto transmit and receive signals in accordance with specificcommunication standards and/or protocols, such as any of the Instituteof Electrical and Electronics Engineers (IEEE) standards including,802.11n-2009, IEEE 802.11-2012, IEEE 802.11-2020, 802.11ay, 802.11ba,802.11ax, and/or 802.11be standards and/or proposed specifications forWLANs, although the scope of embodiments is not limited in this respect.The radio architecture 1300 may also be suitable to transmit and/orreceive communications in accordance with other techniques andstandards.

In some embodiments, the radio architecture 1300 may be configured forhigh-efficiency Wi-Fi (HEW) communications in accordance with the IEEE802.11ax standard. In these embodiments, the radio architecture 1300 maybe configured to communicate in accordance with an OFDMA technique,although the scope of the embodiments is not limited in this respect.

In some other embodiments, the radio architecture 1300 may be configuredto transmit and receive signals transmitted using one or more othermodulation techniques such as spread spectrum modulation (e.g., directsequence code division multiple access (DS-CDMA) and/or frequencyhopping code division multiple access (FH-CDMA)), time-divisionmultiplexing (TDM) modulation, and/or frequency-division multiplexing(FDM) modulation, although the scope of the embodiments is not limitedin this respect.

In some embodiments, as further shown in FIG. 1D, the BT basebandcircuitry 1308 b may be compliant with a Bluetooth (BT) connectivityspecification such as Bluetooth 5.0, or any other iteration of theBluetooth specification.

In some embodiments, the radio architecture 1300 may include other radiocards, such as a cellular radio card configured for cellular (e.g., 5GPPsuch as LTE, LTE-Advanced or 7G communications).

In some IEEE 802.11 embodiments, the radio architecture 1300 may beconfigured for communication over various channel bandwidths includingbandwidths having center frequencies of about 2.4 GHz, 5 GHz, and 6 GHz.The various bandwidths may include bandwidths of about 20 MHz, 40 MHz,80 MHz, 160 MHz, 240 MHz, and 320 MHz with contiguous or non-contiguousbandwidths having increments of 20 MHz, 40 MHz, 80 MHz, 160 MHz, 240MHz, and 320 MHz. The scope of the embodiments is not limited withrespect to the above center frequencies, however.

FIG. 1E illustrates FEM circuitry 1400 such as WLAN FEM circuitry 1304 ashown in FIG. 1 D in accordance with some embodiments. Although theexample of FIG. 1E is described in conjunction with the WLAN FEMcircuitry 1304 a, the example of FIG. 1E may be described in conjunctionwith other configurations such as the BT FEM circuitry 1304 b.

In some embodiments, the FEM circuitry 1400 may include a TX/RX switch1402 to switch between transmit mode and receive mode operation. The FEMcircuitry 1400 may include a receive signal path and a transmit signalpath. The receive signal path of the FEM circuitry 1400 may include alow-noise amplifier (LNA) 1406 to amplify received RF signals 1403 andprovide the amplified received RF signals 1407 as an output (e.g., tothe radio IC circuitry 1306 a-b (FIG. 1D)). The transmit signal path ofthe circuitry 1304 a may include a power amplifier (PA) to amplify inputRF signals 1409 (e.g., provided by the radio IC circuitry 1306 a-b), andone or more filters 1412, such as band-pass filters (BPFs), low-passfilters (LPFs) or other types of filters, to generate RF signals 1415for subsequent transmission (e.g., by one or more of the antennas 1301(FIG. 1D)) via an example duplexer 1414.

In some dual-mode embodiments for Wi-Fi communication, the FEM circuitry1400 may be configured to operate in the 2.4 GHz frequency spectrum, the5 GHz frequency spectrum, or the 6 GHz frequency spectrum. In theseembodiments, the receive signal path of the FEM circuitry 1400 mayinclude a receive signal path duplexer 1404 to separate the signals fromeach spectrum as well as provide a separate LNA 1406 for each spectrumas shown. In these embodiments, the transmit signal path of the FEMcircuitry 1400 may also include a power amplifier 1410 and a filter1412, such as a BPF, an LPF or another type of filter for each frequencyspectrum and a transmit signal path duplexer 1404 to provide the signalsof one of the different spectrums onto a single transmit path forsubsequent transmission by the one or more of the antennas 1301 (FIG.1D). In some embodiments, BT communications may utilize the 2.4 GHzsignal paths and may utilize the same FEM circuitry 1400 as the one usedfor WLAN communications.

FIG. 1F illustrates radio IC circuitry 1506 a in accordance with someembodiments. The radio IC circuitry 1306 a is one example of circuitrythat may be suitable for use as the WLAN or BT radio IC circuitry 1306a/1306 b (FIG. 1D), although other circuitry configurations may also besuitable. Alternatively, the example of FIG. 1F may be described inconjunction with the example BT radio IC circuitry 1306 b.

In some embodiments, the radio IC circuitry 1306 a may include a receivesignal path and a transmit signal path. The receive signal path of theradio IC circuitry 1306 a may include at least mixer circuitry 1502,such as, for example, down-conversion mixer circuitry, amplifiercircuitry 1506 and filter circuitry 1508. The transmit signal path ofthe radio IC circuitry 1306 a may include at least filter circuitry 1512and mixer circuitry 1514, such as, for example, upconversion mixercircuitry. Radio IC circuitry 1306 a may also include synthesizercircuitry 1504 for synthesizing a frequency 1505 for use by the mixercircuitry 1502 and the mixer circuitry 1514. The mixer circuitry 1502and/or 1514 may each, according to some embodiments, be configured toprovide direct conversion functionality. The latter type of circuitrypresents a much simpler architecture as compared with standardsuper-heterodyne mixer circuitries, and any flicker noise brought aboutby the same may be alleviated for example through the use of OFDMmodulation. FIG. 1F illustrates only a simplified version of a radio ICcircuitry, and may include, although not shown, embodiments where eachof the depicted circuitries may include more than one component. Forinstance, mixer circuitry 1514 may each include one or more mixers, andfilter circuitries 1508 and/or 1512 may each include one or morefilters, such as one or more BPFs and/or LPFs according to applicationneeds. For example, when mixer circuitries are of the direct-conversiontype, they may each include two or more mixers.

In some embodiments, mixer circuitry 1502 may be configured todown-convert RF signals 1407 received from the FEM circuitry 1304 a-b(FIG. 1D) based on the synthesized frequency 1505 provided bysynthesizer circuitry 1504. The amplifier circuitry 1506 may beconfigured to amplify the down-converted signals and the filtercircuitry 1508 may include an LPF configured to remove unwanted signalsfrom the down-converted signals to generate output baseband signals1507. Output baseband signals 1507 may be provided to the basebandprocessing circuitry 1308 a-b (FIG. 1D) for further processing. In someembodiments, the output baseband signals 1507 may be zero-frequencybaseband signals, although this is not a requirement. In someembodiments, mixer circuitry 1502 may comprise passive mixers, althoughthe scope of the embodiments is not limited in this respect.

In some embodiments, the mixer circuitry 1514 may be configured toup-convert input baseband signals 1511 based on the synthesizedfrequency 1505 provided by the synthesizer circuitry 1504 to generate RFoutput signals 1409 for the FEM circuitry 1304 a-b. The baseband signals1511 may be provided by the baseband processing circuitry 1308 a-b andmay be filtered by filter circuitry 1512. The filter circuitry 1512 mayinclude an LPF or a BPF, although the scope of the embodiments is notlimited in this respect.

In some embodiments, the mixer circuitry 1502 and the mixer circuitry1514 may each include two or more mixers and may be arranged forquadrature down-conversion and/or upconversion respectively with thehelp of synthesizer 1504. In some embodiments, the mixer circuitry 1502and the mixer circuitry 1514 may each include two or more mixers eachconfigured for image rejection (e.g., Hartley image rejection). In someembodiments, the mixer circuitry 1502 and the mixer circuitry 1514 maybe arranged for direct down-conversion and/or direct upconversion,respectively. In some embodiments, the mixer circuitry 1502 and themixer circuitry 1514 may be configured for super-heterodyne operation,although this is not a requirement.

Mixer circuitry 1502 may comprise, according to one embodiment:quadrature passive mixers (e.g., for the in-phase (I) and quadraturephase (Q) paths). In such an embodiment, RF input signal 1407 from FIG.1F may be down-converted to provide I and Q baseband output signals tobe sent to the baseband processor.

Quadrature passive mixers may be driven by zero and ninety-degreetime-varying LO switching signals provided by a quadrature circuitrywhich may be configured to receive a LO frequency (fLO) from a localoscillator or a synthesizer, such as LO frequency 1505 of synthesizer1504 (FIG. 1F). In some embodiments, the LO frequency may be the carrierfrequency, while in other embodiments, the LO frequency may be afraction of the carrier frequency (e.g., one-half the carrier frequency,one-third the carrier frequency). In some embodiments, the zero andninety-degree time-varying switching signals may be generated by thesynthesizer, although the scope of the embodiments is not limited inthis respect.

In some embodiments, the LO signals may differ in duty cycle (thepercentage of one period in which the LO signal is high) and/or offset(the difference between start points of the period). In someembodiments, the LO signals may have an 85% duty cycle and an 80%offset. In some embodiments, each branch of the mixer circuitry (e.g.,the in-phase (I) and quadrature phase (Q) path) may operate at an 80%duty cycle, which may result in a significant reduction is powerconsumption.

The RF input signal 1407 (FIG. 1E) may comprise a balanced signal,although the scope of the embodiments is not limited in this respect.The I and Q baseband output signals may be provided to low-noiseamplifier, such as amplifier circuitry 1506 (FIG. 1F) or to filtercircuitry 1508 (FIG. 1F).

In some embodiments, the output baseband signals 1507 and the inputbaseband signals 1511 may be analog baseband signals, although the scopeof the embodiments is not limited in this respect. In some alternateembodiments, the output baseband signals 1507 and the input basebandsignals 1511 may be digital baseband signals. In these alternateembodiments, the radio IC circuitry may include analog-to-digitalconverter (ADC) and digital-to-analog converter (DAC) circuitry.

In some dual-mode embodiments, a separate radio IC circuitry may beprovided for processing signals for each spectrum, or for otherspectrums not mentioned here, although the scope of the embodiments isnot limited in this respect.

In some embodiments, the synthesizer circuitry 1504 may be afractional-N synthesizer or a fractional N/N+1 synthesizer, although thescope of the embodiments is not limited in this respect as other typesof frequency synthesizers may be suitable. For example, synthesizercircuitry 1504 may be a delta-sigma synthesizer, a frequency multiplier,or a synthesizer comprising a phase-locked loop with a frequencydivider. According to some embodiments, the synthesizer circuitry 1504may include digital synthesizer circuitry. An advantage of using adigital synthesizer circuitry is that, although it may still includesome analog components, its footprint may be scaled down much more thanthe footprint of an analog synthesizer circuitry. In some embodiments,frequency input into synthesizer circuitry 1504 may be provided by avoltage controlled oscillator (VCO), although that is not a requirement.A divider control input may further be provided by either of thebaseband processing circuitry 1308 a-b (FIG. 1D) depending on thedesired output frequency 1505. In some embodiments, a divider controlinput (e.g., N) may be determined from a look-up table (e.g., within aWi-Fi card) based on a channel number and a channel center frequency asdetermined or indicated by the example application processor 1310. Theapplication processor 1310 may include, or otherwise be connected to,one of the example secure signal converter 101 or the example receivedsignal converter 103 (e.g., depending on which device the example radioarchitecture is implemented in).

In some embodiments, synthesizer circuitry 1504 may be configured togenerate a carrier frequency as the output frequency 1505, while inother embodiments, the output frequency 1505 may be a fraction of thecarrier frequency (e.g., one-half the carrier frequency, one-third thecarrier frequency). In some embodiments, the output frequency 1505 maybe a LO frequency (fLO).

FIG. 1G illustrates a functional block diagram of baseband processingcircuitry 1308 a in accordance with some embodiments. The basebandprocessing circuitry 1308 a is one example of circuitry that may besuitable for use as the baseband processing circuitry 1308 a (FIG. 1D),although other circuitry configurations may also be suitable.Alternatively, the example of FIG. 1F may be used to implement theexample BT baseband processing circuitry 1308 b of FIG. 1D.

The baseband processing circuitry 1308 a may include a receive basebandprocessor (RX BBP) 1602 for processing receive baseband signals 1509provided by the radio IC circuitry 1306 a-b (FIG. 1D) and a transmitbaseband processor (TX BBP) 1604 for generating transmit basebandsignals 1511 for the radio IC circuitry 1306 a-b. The basebandprocessing circuitry 1308 a may also include control logic 1606 forcoordinating the operations of the baseband processing circuitry 1308 a.

In some embodiments (e.g., when analog baseband signals are exchangedbetween the baseband processing circuitry 1308 a-b and the radio ICcircuitry 1306 a-b), the baseband processing circuitry 1308 a mayinclude ADC 1610 to convert analog baseband signals 1609 received fromthe radio IC circuitry 1306 a-b to digital baseband signals forprocessing by the RX BBP 1602. In these embodiments, the basebandprocessing circuitry 1308 a may also include DAC 1612 to convert digitalbaseband signals from the TX BBP 1604 to analog baseband signals 1611.

In some embodiments that communicate OFDM signals or OFDMA signals, suchas through baseband processor 1308 a, the transmit baseband processor1604 may be configured to generate OFDM or OFDMA signals as appropriatefor transmission by performing an inverse fast Fourier transform (IFFT).The receive baseband processor 1602 may be configured to processreceived OFDM signals or OFDMA signals by performing an FFT. In someembodiments, the receive baseband processor 1602 may be configured todetect the presence of an OFDM signal or OFDMA signal by performing anautocorrelation, to detect a preamble, such as a short preamble, and byperforming a cross-correlation, to detect a long preamble. The preamblesmay be part of a predetermined frame structure for Wi-Fi communication.

Referring back to FIG. 1D, in some embodiments, the antennas 1301 (FIG.1D) may each comprise one or more directional or omnidirectionalantennas, including, for example, dipole antennas, monopole antennas,patch antennas, loop antennas, microstrip antennas or other types ofantennas suitable for transmission of RF signals. In some multiple-inputmultiple-output (MIMO) embodiments, the antennas may be effectivelyseparated to take advantage of spatial diversity and the differentchannel characteristics that may result. Antennas 1301 may each includea set of phased-array antennas, although embodiments are not so limited.

Although the radio architecture 1300 is illustrated as having severalseparate functional elements, one or more of the functional elements maybe combined and may be implemented by combinations ofsoftware-configured elements, such as processing elements includingdigital signal processors (DSPs), and/or other hardware elements. Forexample, some elements may comprise one or more microprocessors, DSPs,field-programmable gate arrays (FPGAs), application specific integratedcircuits (ASICs), radio-frequency integrated circuits (RFICs) andcombinations of various hardware and logic circuitry for performing atleast the functions described herein. In some embodiments, thefunctional elements may refer to one or more processes operating on oneor more processing elements.

Some embodiments may be used in conjunction with one or more types ofwireless communication signals and/or systems following one or morewireless communication protocols, for example, radio frequency (RF),infrared (IR), frequency-division multiplexing (FDM), orthogonal FDM(OFDM), time-division multiplexing (TDM), time-division multiple access(TDMA), extended TDMA (E-TDMA), general packet radio service (GPRS),extended GPRS, code-division multiple access (CDMA), wideband CDMA(WCDMA), CDMA 2000, single-carrier CDMA, multi-carrier CDMA,multi-carrier modulation (MDM), discrete multi-tone (DMT), Bluetooth®,global positioning system (GPS), Wi-Fi, Wi-Max, ZigBee, ultra-wideband(UWB), global system for mobile communications (GSM), 2G, 2.5G, 3G,3.5G, 4G, fifth generation (5G) mobile networks, 3GPP, long termevolution (LTE), LTE advanced, enhanced data rates for GSM Evolution(EDGE), or the like. Other embodiments may be used in various otherdevices, systems, and/or networks.

FIGS. 2A-2B illustrate embodiments of a timing measurement TM frame 2000and a fin timing measurement (FTM) frame 2100. FIG. 2A illustrates anembodiment of TM frame 2000. The TM frame 2000 may comprise a vendorspecific element that include an element identifier field, a lengthfield, an organizationally unique number (OUI) or company identification(CID) field, a type field, a followup info field, and apreciseOriginTimestamp field. In some embodiments, thepreciseOriginTimestamp field may include an adjusted leader clock valuewhen the TM frame is transmitted from the leader or an adjusted followerclock value when the TM frame is transmitted from the follower. Theadjusted follower clock value may comprise a sum of the local clock atthe follower and the relative offset of the local clock at the followerfrom the local clock of the leader. The adjusted follower clock valuemay comprise a sum of the local clock at the leader and the relativeoffset of the local clock at the leader from the local clock of thefollower.

Such embodiments may work well if the computed ‘forward sync’ offset isnot large. In further embodiments, the synchronization logic circuitrymay use a servo-based approach to adjust the local clock value inmultiple steps involving smaller jumps. For instance, thesynchronization logic circuitry may:

(a) not start Reverse Sync until the computed offset is smallenough—e.g., include the size of the computed offset as a parameter inthe definition of Stable State.

(b) start the Reverse Sync irrespective of the value of the computedoffset and do not include computed offset to define Stable State. Insuch embodiments, the preciseOriginTimeStamp is not the adjusted localclock but the computed offset may be communicated as a separate value inVendor-Specific (or Standards Organization Specific) information elementin the [Fine] Timing Measurement frames sent in the Reverse direction.

As a comparison, FIG. 2B illustrates an embodiment of a fine timingmanagement (FTM) frame 2100. The FTM frame 2100 may comprise a vendorspecific element that include an element identifier field, a lengthfield, an organizationally unique number (OUI) or company identification(CID) field, a type field, a followup info field, and apreciseOriginTimestamp field. In some embodiments, the FTM frame mayalso include a time synchronization performance information element(TSPIE). The TSPIE may comprise an element identifier field, a lengthfield, an element extension ID field, and a time synchronization errorthreshold field. In some embodiment, the time synchronization errorthreshold field may contain a value that indicates the maximumsynchronization error that a time sensitive application can toleratesuch as 10 nanosecond or 20 nanoseconds.

FIG. 2C illustrates an embodiment of a TM session 2200 between a leaderand a follower. The TM session illustrates the relationship of the MAClayer management entity (MLME) 2212 and the PHY 2214 as well as the MLME2224 and the PHY 2222 with respect to transmitting and receiving the TMframes during the TM session. The MLMEs 2212 and 2224 may instruct thePHY to transmit a TM frame or may parse, interpret and capture valuesfrom TM frames and ACK frames.

The synchronization logic circuitry 2230 of the follower may start theTM session by transmitting a TM frame (R1) for reverse sync at timet_(R)1 and capturing the time t_(R)1. The leader may receive the TMframe (R1) for reverse sync a time t_(R)2. Thereafter, at time t_(F)1,the synchronization logic circuitry 2210 of the leader may transit a TMframe (F1) for forward sync at time t_(F)1 and an acknowledgement (ACK)(R1) at time t_(R)3 in response to the TM frame (R1). The leader mayinclude the times t_(R)2 and t_(R)3 in the ACK (R1). t_(R)2 may be thetime of arrival of the TM frame (R1) at the leader. t_(R)3 may be thetime of departure of the ACK (R1). The inclusion of the times t_(R)2 andt_(R)3 to the follower, provides the follower with information tocalculate an offset between the clock of the leader and the clock of thefollower. Furthermore, the time 2252 may comprise a default time, apreference or setting, or a negotiated time. The time 2252 is the timebetween arrival of the TM frame and transmission of a subsequent frame,which, as a minimum is a short interframe space (SIFS). A SIFS isdefined as the minimum time for the STA to switch from a receiving modeto a transmission mode or vice versa.

The follower may receive the TM frame (F1) at time t_(F)2, and maytransmit a TM frame (R2) at time t¹ _(R)1. The TM frame (R2) may includea calculation of the offset between the leader clock and the clock ofthe follower in a field of the TM frame (R2) and/or the TM frame (R2)may include a calculation of the local clock of the follower plus theoffset between the leader clock and the clock of the follower in a fieldof the TM frame (R2). The leader may receive the TM frame (R2) at timet¹R2. Similarly, after receipt of an ACK (F1) at time t¹F1, the leadermay calculate the offset between the clock of the leader and/or the sumof the offset and the local clock of the leader.

The leader may transmit the TM frame (F2) at time t¹ _(F)1 and thefollower may receive the TM frame at time t1_(F)2. The leader maytransmit the ACK (R2) at time t¹ _(R)3 and the follower may receive theACK (R2) at time t¹ _(R)4.

At the end of the TM session, the follower may transmit an ACK (F2) attime t¹ _(F)3 without transmitting another TM frame. The leader mayreceive the ACK (F2) at time t¹ _(F)4.

FIG. 2D illustrates an embodiment of a FTM session 2300 between a leaderand a follower. The FTM session is similar to the TM session with a fewdifferences. First, synchronization logic circuitry 2230 of the followermay initiate the FTM session by transmitting an initial FTM requestframe. The initial FTM request frame may include parameters for the FTMsession. If the leader accepts the parameters, the leader may transmitan initial FTM request frame that includes or is an indication that theleader accepts the parameters of the FTM session included in the initialFTM request frame from the follower. The leader may follow withtransmission of an ACK frame, and the follower may transmit an ACK framein response to receipt of the initial FTM request frame from the leader.On the other hand, if the leader rejects parameters in the initial FTMrequest frame from the follower, the FTM session ends with he receipt ofthe initial FTM request frame from the follower by the leader.

Second, the FTM session includes the forward sync and reverse sync witha burst of FTM frames rather than TM frames.

FIG. 3 depicts an embodiment of an apparatus to generate, transmit,receive, and interpret or decode PHY frames and MAC frames. Theapparatus comprises a transceiver 3000 coupled with baseband processingcircuitry 3001. The baseband processing circuitry 3001 may comprise aMAC logic circuitry 3091 and PHY logic circuitry 3092. In otherembodiments, the baseband processing circuitry 3001 may be included onthe transceiver 3000.

The MAC logic circuitry 3091 and PHY logic circuitry 3092 may comprisecode executing on processing circuitry of a baseband processingcircuitry 3001; circuitry to implement operations of functionality ofthe MAC or PHY; or a combination of both. In the present embodiment, theMAC logic circuitry 3091 and PHY logic circuitry 3092 may comprisesynchronization logic circuitry 3093 to implement perform timesynchronization and the determine a synchronization error based on thetime synchronization to gauge performance of the time synchronization.

The MAC logic circuitry 3091 may determine a frame such as a MAC controlframe and the PHY logic circuitry 3092 may determine the physical layerprotocol data unit (PPDU) by prepending the frame, also called a MACprotocol data unit (MPDU), with a physical layer (PHY) preamble fortransmission of the MAC control frame via the antenna array 3018 andcause transmission of the MAC control frame in the PPDU.

The transceiver 3000 comprises a receiver 3004 and a transmitter 3006.Embodiments have many different combinations of modules to process databecause the configurations are deployment specific. FIG. 3 illustratessome of the modules that are common to many embodiments. In someembodiments, one or more of the modules may be implemented in circuitryseparate from the baseband processing circuitry 3001. In someembodiments, the baseband processing circuitry 3001 may execute code inprocessing circuitry of the baseband processing circuitry 3001 toimplement one or more of the modules.

In the present embodiment, the transceiver 3000 also includes WURcircuitry 3110 and 3120 such as the WUR circuitry 1024 and 1054,respectively, shown in FIG. 1A. The WUR circuitry 3110 may comprisecircuitry to use portions of the transmitter 3006 (a transmitter of thewireless communications I/F) to generate a WUR packet. For instance, theWUR circuitry 3110 may generate, e.g., an OOK signal with OFDM symbolsto generate a WUR packet for transmission via the antenna array 3018. Inother embodiments, the WUR may comprise an independent circuitry thatdoes not use portions of the transmitter 3006.

Note that a station such as the STA 1210 in FIG. 1C may comprisemultiple transmitters to facilitate concurrent transmissions on multiplecontiguous and/or non-contiguous carrier frequencies.

The transmitter 3006 may comprise one or more of or all the modulesincluding an encoder 3008, a stream deparser 3066, a frequency segmentparser 3007, an interleaver 3009, a modulator 3010, a frequency segmentdeparser 3060, an OFDM 3012, an Inverse Fast Fourier Transform (IFFT)module 3015, a GI module 3045, and a transmitter front end 3040. Theencoder 3008 of transmitter 3006 receives and encodes a data streamdestined for transmission from the MAC logic circuitry 3091 with, e.g.,a binary convolutional coding (BCC), a low-density parity check coding(LDPC), and/or the like. After coding, scrambling, puncturing andpost-FEC (forward error correction) padding, a stream parser 3064 mayoptionally divide the data bit streams at the output of the FEC encoderinto groups of bits. The frequency segment parser 3007 may receive datastream from encoder 3008 or streams from the stream parser 3064 andoptionally parse each data stream into two or more frequency segments tobuild a contiguous or non-contiguous bandwidth based upon smallerbandwidth frequency segments. The interleaver 3009 may interleave rowsand columns of bits to prevent long sequences of adjacent noisy bitsfrom entering a BCC decoder of a receiver.

The modulator 3010 may receive the data stream from interleaver 3009 andmay impress the received data blocks onto a sinusoid of a selectedfrequency for each stream via, e.g., mapping the data blocks into acorresponding set of discrete amplitudes of the sinusoid, or a set ofdiscrete phases of the sinusoid, or a set of discrete frequency shiftsrelative to the frequency of the sinusoid. In some embodiments, theoutput of modulator 3010 may optionally be fed into the frequencysegment deparser 3060 to combine frequency segments in a single,contiguous frequency bandwidth of, e.g., 320 MHz. Other embodiments maycontinue to process the frequency segments as separate data streams for,e.g., a non-contiguous 160+160 MHz bandwidth transmission.

After the modulator 3010, the data stream(s) are fed to an OFDM 3012.The OFDM 3012 may comprise a space-time block coding (STBC) module 3011,and a digital beamforming (DBF) module 3014. The STBC module 3011 mayreceive constellation points from the modulator 3010 corresponding toone or more spatial streams and may spread the spatial streams to agreater number of space-time streams. Further embodiments may omit theSTBC.

The OFDM 3012 impresses or maps the modulated data formed as OFDMsymbols onto a plurality of orthogonal subcarriers, so the OFDM symbolsare encoded with the subcarriers or tones. The OFDM symbols may be fedto the DBF module 3014. Generally, digital beam forming uses digitalsignal processing algorithms that operate on the signals received by,and transmitted from, an array of antenna elements. Transmit beamformingprocesses the channel state to compute a steering matrix that is appliedto the transmitted signal to optimize reception at one or morereceivers. This is achieved by combining elements in a phased antennaarray in such a way that signals at particular angles experienceconstructive interference while others experience destructiveinterference.

The IFFT module 3015 may perform an inverse discrete Fourier transform(IDFT) on the OFDM symbols to map on the subcarriers. The guard interval(GI) module 3045 may insert guard intervals by prepending to the symbola circular extension of itself. The GI module 3045 may also comprisewindowing to optionally smooth the edges of each symbol to increasespectral decay.

The output of the GI module 3045 may enter the radio 3042 to convert thetime domain signals into radio signals by combining the time domainsignals with subcarrier frequencies to output into the transmitter frontend module (TX FEM) 3040. The transmitter front end 3040 may comprise awith a power amplifier (PA) 3044 to amplify the signal and prepare thesignal for transmission via the antenna array 3018. In many embodiments,entrance into a spatial reuse mode by a communications device such as astation or AP may reduce the amplification by the PA 3044 to reducechannel interference caused by transmissions.

The transceiver 3000 may also comprise duplexers 3016 connected toantenna array 3018. The antenna array 3018 radiates the informationbearing signals into a time-varying, spatial distribution ofelectromagnetic energy that can be received by an antenna of a receiver.In several embodiments, the receiver 3004 and the transmitter 3006 mayeach comprise its own antenna(s) or antenna array(s).

The transceiver 3000 may comprise a receiver 3004 for receiving,demodulating, and decoding information bearing communication signals.The receiver 3004 may comprise a receiver front-end module (RX FEM) 3050to detect the signal, detect the start of the packet, remove the carrierfrequency, and amplify the subcarriers via a low noise amplifier (LNA)3054 to output to the radio 3052. The radio 3052 may convert the radiosignals into time domain signals to output to the GI module 3055 byremoving the subcarrier frequencies from each tone of the radio signals.

The receiver 3004 may comprise a GI module 3055 and a fast Fouriertransform (FFT) module 3019. The GI module 3055 may remove the guardintervals and the windowing and the FFT module 3019 may transform thecommunication signals from the time domain to the frequency domain.

The receiver 3004 may also comprise an OFDM 3022, a frequency segmentparser 3062, a demodulator 3024, a deinterleaver 3025, a frequencysegment deparser 3027, a stream deparser 3066, and a decoder 3026. Anequalizer may output the weighted data signals for the OFDM packet tothe OFDM 3022. The OFDM 3022 extracts signal information as OFDM symbolsfrom the plurality of subcarriers onto which information-bearingcommunication signals are modulated.

The OFDM 3022 may comprise a DBF module 3020, and an STBC module 3021.The received signals are fed from the equalizer to the DBF module 3020.The DBF module 3020 may comprise algorithms to process the receivedsignals as a directional transmission directed toward to the receiver3004. And the STBC module 3021 may transform the data streams from thespace-time streams to spatial streams.

The output of the STBC module 3021 may enter a frequency segment parser3062 if the communication signal is received as a single, contiguousbandwidth signal to parse the signal into, e.g., two or more frequencysegments for demodulation and deinterleaving.

The demodulator 3024 demodulates the spatial streams. Demodulation isthe process of extracting data from the spatial streams to producedemodulated spatial streams. The deinterleaver 3025 may deinterleave thesequence of bits of information. The frequency segment deparser 3027 mayoptionally deparse frequency segments as received if received asseparate frequency segment signals or may deparse the frequency segmentsdetermined by the optional frequency segment parser 3062. The decoder3026 decodes the data from the demodulator 3024 and transmits thedecoded information, the MPDU, to the MAC logic circuitry 3091.

The MAC logic circuitry 3091 may parse the MPDU based upon a formatdefined in the communications device for a frame to determine theparticular type of frame by determining the type value and the subtypevalue. The MAC logic circuitry 3091 may then interpret the remainder ofMPDU.

While the description of FIG. 3 focuses primarily on a single spatialstream system for simplicity, many embodiments are capable of multiplespatial stream transmissions and use parallel data processing paths formultiple spatial streams from the PHY logic circuitry 3092 through totransmission. Further embodiments may include the use of multipleencoders to afford implementation flexibility.

FIG. 4A depicts an embodiment of a flowchart 4000 to implementsynchronization logic circuitry such as the synchronization logiccircuitry discussed in FIGS. 1-3. At element 4010, synchronization logiccircuitry of leader (e.g., the synchronization logic circuitry 1220 ofthe AP MLD 1210) may receive a first set of two or more timingmanagement frames wherein one or more of the two or more timingmanagement frames in the first set comprise a first adjusted followerclock value. The first set of two or more timing management frames maycomprise part of a reverse sync.

At element 4015, synchronization logic circuitry of leader may causetransmission of a second set of two or more timing management frames,wherein one or more of the two or more timing management frames in thesecond set comprise a second adjusted clock value. The second set of twoor more timing management frames may comprise part of a forward sync. Insome embodiments, the TM frames of the two set may be interleaved suchas the TM frames shown in FIG. 2C. In other embodiments, theinterleaving may be performed in a different pattern such as two forwardsync TM frames for each reverse sync TM frame, or vice versa.

At element 4020, synchronization logic circuitry of leader may causetransmission of a first set of two or more acknowledgement frames. Andat element 4025, synchronization logic circuitry of leader may receive asecond set of two or more acknowledgement frames. Note that these framesmay be interleaved with the first and second sets of TM frames based onthe interleaving of the TM frames. It is understood that the abovedescriptions are for purposes of illustration and are not meant to belimiting.

At element 4030, synchronization logic circuitry of leader may calculatea second adjusted clock value. At element 4035, synchronization logiccircuitry of leader may calculate a difference between the firstadjusted follower clock value and the second adjusted clock value todetermine a synchronization error, the synchronization error torepresent a performance of the time synchronization. In someembodiments, the first adjusted follower clock value comprising a sum ofthe local clock at the follower and the relative offset of the localclock at the follower from the local clock of the leader and the secondadjusted clock value comprising a sum of the local clock at the leaderand the relative offset of the local clock at the leader from the localclock of the follower. In some embodiments, calculation of thedifference comprises calculation in response to receipt of eachacknowledgement in the second set of acknowledgement frames.

In some embodiments, the synchronization logic circuitry may furtherreceive a first initial fine timing management frame, cause transmissionof a second initial fine timing frame in response to receipt of thefirst fine timing management frame, cause transmission of anacknowledgement in response to receipt of the first fine timingmanagement frame, and receive an acknowledgement in response to thetransmission of a second initial fine timing frame. In other words, theTM session may be an FTM session or at least the forward sync or thereverse sync may include FTM frames. In such embodiments, the first finetiming management frame comprises parameters including a number of timemanagement frames in the first and second sets of time managementframes, a time interval between transmission of time management framesin the first and second sets of time management frames, and a bandwidthof a channel used for transmission of the first and second sets of timemanagement frames.

FIG. 4B depicts another embodiment of a flowchart 4100 to implementsynchronization logic circuitry. At element 4110, synchronization logiccircuitry of a follower (e.g., the synchronization logic circuitry 1250of MLD STA 1230 shown FIG. 1C) may cause transmission of a first set oftwo or more timing management frames wherein one or more of the two ormore timing management frames in the first set comprise a first adjustedleader clock value.

At element 4115, the follower may receive a second set of two or moretiming management frames, wherein one or more of the two or more timingmanagement frames in the second set comprise a second adjusted clockvalue. In some embodiments, the synchronization logic circuitry mayfurther receive a first initial fine timing management frame, causetransmission of a second initial fine timing frame in response toreceipt of the first fine timing management frame, cause transmission ofan acknowledgement in response to receipt of the first fine timingmanagement frame, and receive an acknowledgement in response to thetransmission of a second initial fine timing frame.

In element 4120, the follower may receive a first set of two or moreacknowledgement frames. In element 4125, the follower may calculate thesecond adjusted clock value. In some embodiments, the first adjustedleader clock value may comprise a sum of the local clock at the leaderand the relative offset of the local clock at the leader from the localclock of the follower and the second adjusted clock value may comprise asum of the local clock at the follower and the relative offset of thelocal clock at the follower from the local clock of the leader.

In element 4130, the follower may cause transmission of a second set oftwo or more acknowledgement frames. In some embodiments, the time framebetween receipt of a time management frame in the first set of timemanagement frames and transmission of a time management frame in thesecond set of time management frames is a minimum of a short interframespace

In element 4135, the follower may calculate a difference between thefirst adjusted leader clock value and the second adjusted clock value todetermine a synchronization error, the synchronization error torepresent a performance of the time synchronization.

FIGS. 4C-D depict embodiments of flowcharts 4300 and 4410 to transmit,receive, and interpret communications with a frame. Referring to FIG.4C, the flowchart 4300 may begin with receiving an MU frame from thewireless communications I/F 1216 of the STA 1210 by the wirelesscommunications I/Fs (such as wireless communications I/F 1246 of the STA1230, STA 1290, STA 1292, and STA 1296 as shown in FIG. 1C. The MAClayer logic circuitry, such as the MAC logic circuitry 3091 in FIG. 1C,of each STA of STA 1230, STA 1290, STA 1292, and STA 1296 may generate acontrol frame responsive to the MU frame to transmit to the STA 1210 asa control frame to the STA 1210 and may pass the frame as an MACprotocol data unit (MPDU) to a PHY logic circuitry such as the PHY logiccircuitry 3092 in FIG. 1C. The PHY logic circuitry may also encode andtransform the PPDU into OFDM symbols for transmission to the STA 1210.The PHY logic circuitry may generate a preamble to prepend the PHYservice data unit (PSDU) (the MPDU) to form a PHY protocol data unit(PPDU) for transmission (element 4310).

The physical layer device such as the transmitter 3006 in FIG. 3 or thewireless network interfaces 1222 and 1252 in FIG. 1A may convert thePPDU to a communication signal via a radio (element 4315). Thetransmitter may then transmit the communication signal via the antennacoupled with the radio (element 4320).

Referring to FIG. 4D, the flowchart 4410 begins with a receiver of adevice such as the receiver 3004 in FIG. 3 receiving a communicationsignal via one or more antenna(s) such as an antenna element of antennaarray 3018 (element 4420). The receiver may convert the communicationsignal into an MPDU in accordance with the process described in thepreamble (element 4425). More specifically, the received signal is fedfrom the one or more antennas to a DBF such as the DBF 220. The DBFtransforms the antenna signals into information signals. The output ofthe DBF is fed to OFDM such as the OFDM 3022 in FIG. 3. The OFDMextracts signal information from the plurality of subcarriers onto whichinformation-bearing signals are modulated. Then, the demodulator such asthe demodulator 3024 demodulates the signal information via, e.g., BPSK,16-QAM (quadrature amplitude modulation), 64-QAM, 256-QAM, 1024-QAM, or4096-QAM with a forward error correction (FEC) coding rate (1/2, 2/3,3/4, or 5/6). And the decoder such as the decoder 3026 decodes thesignal information from the demodulator via, e.g., BCC or LDPC, toextract the MPDU and pass or communicate the MPDU to MAC layer logiccircuitry such as MAC logic circuitry 3091 (element 4420).

The MAC logic circuitry may determine frame field values from the MPDU(element 4425) such as the control frame fields in the control frameshown in FIG. 2F. For instance, the MAC logic circuitry may determineframe field values such as the type and subtype field values of thecontrol frame. The MAC logic circuitry may determine that the MPDUcomprises a control frame so the MAC logic circuitry may generate aframe in response if the sub-band of the channel is clear according to adirectional CCA.

FIG. 5 shows a functional diagram of an exemplary communication station500, in accordance with one or more example embodiments of the presentdisclosure. In one embodiment, FIG. 5 illustrates a functional blockdiagram of a communication station that may be suitable for use as an AP1005 (FIG. 1A) or a user device 1028 (FIG. 1A) in accordance with someembodiments. The communication station 500 may also be suitable for useas other user device(s) 1020 such as the user devices 1024 and/or 1026.The user devices 1024 and/or 1026 may include, e.g., a handheld device,a mobile device, a cellular telephone, a smartphone, a tablet, anetbook, a wireless terminal, a laptop computer, a wearable computerdevice, a femtocell, a high data rate (HDR) subscriber station, anaccess point, an access terminal, or other personal communication system(PCS) device.

The communication station 500 may include communications circuitry 502and a transceiver 510 for transmitting and receiving signals to and fromother communication stations using one or more antennas 501. Thecommunications circuitry 502 may include circuitry that can operate thephysical layer (PHY) communications and/or medium access control (MAC)communications for controlling access to the wireless medium, and/or anyother communications layers for transmitting and receiving signals. Thecommunication station 500 may also include processing circuitry 506 andmemory 508 arranged to perform the operations described herein. In someembodiments, the communications circuitry 502 and the processingcircuitry 506 may be configured to perform operations detailed in theabove figures, diagrams, and flows.

In accordance with some embodiments, the communications circuitry 502may be arranged to contend for a wireless medium and configure frames orpackets for communicating over the wireless medium. The communicationscircuitry 502 may be arranged to transmit and receive signals. Thecommunications circuitry 502 may also include circuitry formodulation/demodulation, upconversion/downconversion, filtering,amplification, etc. In some embodiments, the processing circuitry 506 ofthe communication station 500 may include one or more processors. Inother embodiments, two or more antennas 501 may be coupled to thecommunications circuitry 502 arranged for sending and receiving signals.The memory 508 may store information for configuring the processingcircuitry 506 to perform operations for configuring and transmittingmessage frames and performing the various operations described herein.The memory 508 may include any type of memory, including non-transitorymemory, for storing information in a form readable by a machine (e.g., acomputer). For example, the memory 508 may include a computer-readablestorage device, read-only memory (ROM), random-access memory (RAM),magnetic disk storage media, optical storage media, flash-memory devicesand other storage devices and media.

In some embodiments, the communication station 500 may be part of aportable wireless communication device, such as a personal digitalassistant (PDA), a laptop or portable computer with wirelesscommunication capability, a web tablet, a wireless telephone, asmartphone, a wireless headset, a pager, an instant messaging device, adigital camera, an access point, a television, a medical device (e.g., aheart rate monitor, a blood pressure monitor, etc.), a wearable computerdevice, or another device that may receive and/or transmit informationwirelessly.

In some embodiments, the communication station 500 may include one ormore antennas 501. The antennas 501 may include one or more directionalor omnidirectional antennas, including, for example, dipole antennas,monopole antennas, patch antennas, loop antennas, microstrip antennas,or other types of antennas suitable for transmission of RF signals. Insome embodiments, instead of two or more antennas, a single antenna withmultiple apertures may be used. In these embodiments, each aperture maybe considered a separate antenna. In some multiple-input multiple-output(MIMO) embodiments, the antennas may be effectively separated forspatial diversity and the different channel characteristics that mayresult between each of the antennas and the antennas of a transmittingstation.

In some embodiments, the communication station 500 may include one ormore of a keyboard, a display, a non-volatile memory port, multipleantennas, a graphics processor, an application processor, speakers, andother mobile device elements. The display may be an LCD screen includinga touch screen.

Although the communication station 500 is illustrated as having severalseparate functional elements, two or more of the functional elements maybe combined and may be implemented by combinations ofsoftware-configured elements, such as processing elements includingdigital signal processors (DSPs), and/or other hardware elements. Forexample, some elements may include one or more microprocessors, DSPs,field-programmable gate arrays (FPGAs), application specific integratedcircuits (ASICs), radio-frequency integrated circuits (RFICs) andcombinations of various hardware and logic circuitry for performing atleast the functions described herein. In some embodiments, thefunctional elements of the communication station 500 may refer to one ormore processes operating on one or more processing elements.

Certain embodiments may be implemented in one or a combination ofhardware, firmware, and software. Other embodiments may also beimplemented as instructions stored on a computer-readable storagedevice, which may be read and executed by at least one processor toperform the operations described herein. A computer-readable storagedevice may include any non-transitory memory mechanism for storinginformation in a form readable by a machine (e.g., a computer). Forexample, a computer-readable storage device may include read-only memory(ROM), random-access memory (RAM), magnetic disk storage media, opticalstorage media, flash-memory devices, and other storage devices andmedia. In some embodiments, the communication station 500 may includeone or more processors and may be configured with instructions stored ona computer-readable storage device.

FIG. 6 illustrates a block diagram of an example of a machine 600 orsystem upon which any one or more of the techniques (e.g.,methodologies) discussed herein may be performed. For instance, themachine may comprise an AP such as the AP 1005 and/or one of the userdevices 1020 shown in FIG. 1A. In other embodiments, the machine 600 mayoperate as a standalone device or may be connected (e.g., networked) toother machines. In a networked deployment, the machine 600 may operatein the capacity of a server machine, a client machine, or both inserver-client network environments. In an example, the machine 600 mayact as a peer machine in peer-to-peer (P2P) (or other distributed)network environments. The machine 600 may be a personal computer (PC), atablet PC, a set-top box (STB), a personal digital assistant (PDA), amobile telephone, a wearable computer device, a web appliance, a networkrouter, a switch or bridge, or any machine capable of executinginstructions (sequential or otherwise) that specify actions to be takenby that machine, such as a base station. Further, while only a singlemachine is illustrated, the term “machine” shall also be taken toinclude any collection of machines that individually or jointly executea set (or multiple sets) of instructions to perform any one or more ofthe methodologies discussed herein, such as cloud computing, software asa service (SaaS), or other computer cluster configurations.

Examples, as described herein, may include or may operate on logic or anumber of components, modules, or mechanisms. Modules are tangibleentities (e.g., hardware) capable of performing specified operationswhen operating. A module includes hardware. In an example, the hardwaremay be specifically configured to carry out a specific operation (e.g.,hardwired). In another example, the hardware may include configurableexecution units (e.g., transistors, circuits, etc.) and a computerreadable medium containing instructions where the instructions configurethe execution units to carry out a specific operation when in operation.The configuring may occur under the direction of the execution units ora loading mechanism. Accordingly, the execution units arecommunicatively coupled to the computer-readable medium when the deviceis operating. In this example, the execution units may be a member ofmore than one module. For example, under operation, the execution unitsmay be configured by a first set of instructions to implement a firstmodule at one point in time and reconfigured by a second set ofinstructions to implement a second module at a second point in time.

The machine (e.g., computer system) 600 may include a hardware processor602 (e.g., a central processing unit (CPU), a graphics processing unit(GPU), a hardware processor core, or any combination thereof), a mainmemory 604 and a static memory 606, some or all of which may communicatewith each other via one or more interlinks (e.g., buses or high speedinterconnects) 608. Note that the single set of interlinks 608 may berepresentative of the physical interlinks in some embodiments but is notrepresentative of the physical interlinks 608 in other embodiments. Forexample, the main memory 604 may couple directly with the hardwareprocessor 602 via high speed interconnects or a main memory bus. Thehigh speed interconnects typically connect two devices, and the bus isgenerally designed to interconnect two or more devices and include anarbitration scheme to provide fair access to the bus by the two or moredevices.

The machine 600 may further include a power management device 632, agraphics display device 610, an alphanumeric input device 612 (e.g., akeyboard), and a user interface (UI) navigation device 614 (e.g., amouse). In an example, the graphics display device 610, alphanumericinput device 612, and UI navigation device 614 may be a touch screendisplay. The machine 600 may additionally include a storage device(i.e., drive unit) 616, a signal generation device 618 (e.g., aspeaker), a synchronization logic circuitry 619, a network interfacedevice/transceiver 620 coupled to antenna(s) 630, and one or moresensors 628, such as a global positioning system (GPS) sensor, acompass, an accelerometer, or other sensor. The machine 600 may includean output controller 634, such as a serial (e.g., universal serial bus(USB), parallel, or other wired or wireless (e.g., infrared (IR), nearfield communication (NFC), etc.) connection to communicate with orcontrol one or more peripheral devices (e.g., a printer, a card reader,etc.)). The operations in accordance with one or more exampleembodiments of the present disclosure may be carried out by a basebandprocessor such as the baseband processing circuitry 1218 and/or 1248shown in FIG. 1C. The baseband processor may be configured to generatecorresponding baseband signals. The baseband processor may furtherinclude physical layer (PHY) and medium access control layer (MAC)circuitry, and may further interface with the hardware processor 602 forgeneration and processing of the baseband signals and for controllingoperations of the main memory 604, the storage device 616, and/or thesynchronization logic circuitry 619. The baseband processor may beprovided on a single radio card, a single chip, or an integrated circuit(IC).

The storage device 616 may include a machine readable medium 622 onwhich is stored one or more sets of data structures or instructions 624(e.g., software) embodying or utilized by any one or more of thetechniques or functions described herein. The instructions 624 may alsoreside, completely or at least partially, within the main memory 604,within the static memory 606, or within the hardware processor 602during execution thereof by the machine 600. In an example, one or anycombination of the hardware processor 602, the main memory 604, thestatic memory 606, or the storage device 616 may constitutemachine-readable media.

The synchronization logic circuitry 619 may carry out or perform any ofthe operations and processes in relation to monitoring timesynchronization by a retiming measurement frame transmitted by an AP MLDacting as a channel enabler for a first STA in a 2.4 GHz, 5 GHz, or 6GHz channel or the like (e.g., flowchart 4000 shown in FIG. 4A,flowchart 4100 shown in FIG. 4B, and flowchart 4200 shown in FIG. 4C)described and shown above. It is understood that the above are only asubset of what the synchronization logic circuitry 619 may be configuredto perform and that other functions included throughout this disclosuremay also be performed by the synchronization logic circuitry 619.

While the machine-readable medium 622 is illustrated as a single medium,the term “machine-readable medium” may include a single medium ormultiple media (e.g., a centralized or distributed database, and/orassociated caches and servers) configured to store the one or moreinstructions 624.

Various embodiments may be implemented fully or partially in softwareand/or firmware. This software and/or firmware may take the form ofinstructions contained in or on a non-transitory computer-readablestorage medium. Those instructions may then be read and executed by oneor more processors to enable performance of the operations describedherein. The instructions may be in any suitable form, such as but notlimited to source code, compiled code, interpreted code, executablecode, static code, dynamic code, and the like. Such a computer-readablemedium may include any tangible non-transitory medium for storinginformation in a form readable by one or more computers, such as but notlimited to read only memory (ROM); random access memory (RAM); magneticdisk storage media; optical storage media; a flash memory, etc.

The term “machine-readable medium” may include any medium that iscapable of storing, encoding, or carrying instructions for execution bythe machine 600 and that cause the machine 600 to perform any one ormore of the techniques of the present disclosure, or that is capable ofstoring, encoding, or carrying data structures used by or associatedwith such instructions. Non-limiting machine-readable medium examplesmay include solid-state memories and optical and magnetic media. In anexample, a massed machine-readable medium includes a machine-readablemedium with a plurality of particles having resting mass. Specificexamples of massed machine-readable media may include non-volatilememory, such as semiconductor memory devices (e.g., electricallyprogrammable read-only memory (EPROM), or electrically erasableprogrammable read-only memory (EEPROM)) and flash memory devices;magnetic disks, such as internal hard disks and removable disks;magneto-optical disks; and CD-ROM and DVD-ROM disks.

The instructions 624 may further be transmitted or received over acommunications network 626 using a transmission medium via the networkinterface device/transceiver 620 utilizing any one of a number oftransfer protocols (e.g., frame relay, internet protocol (IP),transmission control protocol (TCP), user datagram protocol (UDP),hypertext transfer protocol (HTTP), etc.). Example communicationsnetworks may include a local area network (LAN), a wide area network(WAN), a packet data network (e.g., the Internet), mobile telephonenetworks (e.g., cellular networks), plain old telephone (POTS) networks,wireless data networks (e.g., Institute of Electrical and ElectronicsEngineers (IEEE) 802.11 family of standards known as Wi-Fi®, IEEE 802.16family of standards known as WiMax®), IEEE 802.15.4 family of standards,and peer-to-peer (P2P) networks, among others. In an example, thenetwork interface device/transceiver 620 may include one or morephysical jacks (e.g., Ethernet, coaxial, or phone jacks) or one or moreantennas to connect to the communications network 626. In an example,the network interface device/transceiver 620 may include a plurality ofantennas to wirelessly communicate using at least one of single-inputmultiple-output (SIMO), multiple-input multiple-output (MIMO), ormultiple-input single-output (MISO) techniques. The term “transmissionmedium” shall be taken to include any intangible medium that is capableof storing, encoding, or carrying instructions for execution by themachine 600 and includes digital or analog communications signals orother intangible media to facilitate communication of such software.

The operations and processes described and shown above may be carriedout or performed in any suitable order as desired in variousimplementations. Additionally, in certain implementations, at least aportion of the operations may be carried out in parallel. Furthermore,in certain implementations, less than or more than the operationsdescribed may be performed.

FIG. 7 illustrates an example of a storage medium 7000 to storeassessment logic such as logic to implement the synchronization logiccircuitry 619 shown in FIG. 6 and/or the other logic discussed hereinperform resource assessment for P2P STAs. Storage medium 7000 maycomprise an article of manufacture. In some examples, storage medium7000 may include any non-transitory computer readable medium ormachine-readable medium, such as an optical, magnetic or semiconductorstorage. Storage medium 7000 may store diverse types of computerexecutable instructions, such as instructions to implement logic flowsand/or techniques described herein. Examples of a computer readable ormachine-readable storage medium may include any tangible media capableof storing electronic data, including volatile memory or non-volatilememory, removable or non-removable memory, erasable or non-erasablememory, writeable or re-writeable memory, and so forth. Examples ofcomputer executable instructions may include any suitable type of code,such as source code, compiled code, interpreted code, executable code,static code, dynamic code, object-oriented code, visual code, and thelike.

FIG. 8 illustrates an example computing platform 8000 such as the MLDSTAs 1210, 1230, 1290, 1292, 1294, 1296, and 1298 in FIG. 1A. In someexamples, as shown in FIG. 8, computing platform 8000 may include aprocessing component 8010, other platform components or a communicationsinterface 8030 such as the wireless network interfaces 1222 and 1252shown in FIG. 1A. According to some examples, computing platform 8000may be a computing device such as a server in a system such as a datacenter or server farm that supports a manager or controller for managingconfigurable computing resources as mentioned above.

According to some examples, processing component 8010 may executeprocessing operations or logic for apparatus 8015 described herein.Processing component 8010 may include various hardware elements,software elements, or a combination of both. Examples of hardwareelements may include devices, logic devices, components, processors,microprocessors, circuits, processor circuits, circuit elements (e.g.,transistors, resistors, capacitors, inductors, and so forth), integratedcircuits (ICs), application specific integrated circuits (ASIC),programmable logic devices (PLD), digital signal processors (DSP), fieldprogrammable gate array (FPGA), memory units, logic gates, registers,semiconductor device, chips, microchips, chip sets, and so forth.Examples of software elements, which may reside in the storage medium8020, may include software components, programs, applications, computerprograms, application programs, device drivers, system programs,software development programs, machine programs, operating systemsoftware, middleware, firmware, software modules, routines, subroutines,functions, methods, procedures, software interfaces, application programinterfaces (API), instruction sets, computing code, computer code, codesegments, computer code segments, words, values, symbols, or anycombination thereof. While discussions herein describe elements ofembodiments as software elements and/or hardware elements, decisions toimplement an embodiment using hardware elements and/or software elementsmay vary in accordance with any number of design considerations orfactors, such as desired computational rate, power levels, heattolerances, processing cycle budget, input data rates, output datarates, memory resources, data bus speeds and other design or performanceconstraints.

In some examples, other platform components 8025 may include commoncomputing elements, such as one or more processors, multi-coreprocessors, co-processors, memory units, chipsets, controllers,peripherals, interfaces, oscillators, timing devices, video cards, audiocards, multimedia input/output (I/O) components (e.g., digitaldisplays), power supplies, and so forth. Examples of memory units mayinclude without limitation various types of computer readable andmachine readable storage media in the form of one or more higher speedmemory units, such as read-only memory (ROM), random-access memory(RAM), dynamic RAM (DRAM), Double-Data-Rate DRAM (DDRAM), synchronousDRAM (SDRAM), static RAM (SRAM), programmable ROM (PROM), erasableprogrammable ROM (EPROM), electrically erasable programmable ROM(EEPROM), flash memory, polymer memory such as ferroelectric polymermemory, ovonic memory, phase change or ferroelectric memory,silicon-oxide-nitride-oxide-silicon (SONOS) memory, magnetic or opticalcards, an array of devices such as Redundant Array of Independent Disks(RAID) drives, solid state memory devices (e.g., universal serial bus(USB) memory), solid state drives (SSD) and any other type of storagemedia suitable for storing information.

In some examples, communications interface 8030 may include logic and/orfeatures to support a communication interface. For these examples,communications interface 8030 may include one or more communicationinterfaces that operate according to various communication protocols orstandards to communicate over direct or network communication links.Direct communications may occur via use of communication protocols orstandards described in one or more industry standards (includingprogenies and variants) such as those associated with the PeripheralComponent Interconnect (PCI) Express specification. Networkcommunications may occur via use of communication protocols or standardssuch as those described in one or more Ethernet standards promulgated bythe Institute of Electrical and Electronics Engineers (IEEE). Forexample, one such Ethernet standard may include IEEE 802.3-2012, Carriersense Multiple access with Collision Detection (CSMA/CD) Access Methodand Physical Layer Specifications, Published in December 2012(hereinafter “IEEE 802.3”). Network communication may also occuraccording to one or more OpenFlow specifications such as the OpenFlowHardware Abstraction API Specification. Network communications may alsooccur according to Infiniband Architecture Specification, Volume 1,Release 1.3, published in March 2015 (“the Infiniband Architecturespecification”).

Computing platform 8000 may be part of a computing device that may be,for example, a server, a server array or server farm, a web server, anetwork server, an Internet server, a workstation, a mini-computer, amain frame computer, a supercomputer, a network appliance, a webappliance, a distributed computing system, multiprocessor systems,processor-based systems, or combination thereof. Accordingly, variousembodiments of the computing platform 8000 may include or excludefunctions and/or specific configurations of the computing platform 8000described herein.

The components and features of computing platform 8000 may comprise anycombination of discrete circuitry, ASICs, logic gates and/or single chiparchitectures. Further, the features of computing platform 8000 maycomprise microcontrollers, programmable logic arrays and/ormicroprocessors or any combination of the foregoing where suitablyappropriate. Note that hardware, firmware and/or software elements maybe collectively or individually referred to herein as “logic”.

One or more aspects of at least one example may comprise representativeinstructions stored on at least one machine-readable medium whichrepresents various logic within the processor, which when read by amachine, computing device or system causes the machine, computing deviceor system to fabricate logic to perform the techniques described herein.Such representations, known as “IP cores” may be stored on a tangible,machine readable medium and supplied to various customers ormanufacturing facilities to load into the fabrication machines that makethe logic or processor.

Some examples may include an article of manufacture or at least onecomputer-readable medium. A computer-readable medium may include anon-transitory storage medium to store logic. In some examples, thenon-transitory storage medium may include one or more types ofcomputer-readable storage media capable of storing electronic data,including volatile memory or non-volatile memory, removable ornon-removable memory, erasable or non-erasable memory, writeable orre-writeable memory, and so forth. In some examples, the logic mayinclude various software elements, such as software components,programs, applications, computer programs, application programs, systemprograms, machine programs, operating system software, middleware,firmware, software modules, routines, subroutines, functions, methods,procedures, software interfaces, API, instruction sets, computing code,computer code, code segments, computer code segments, words, values,symbols, or any combination thereof.

According to some examples, a computer-readable medium may include anon-transitory storage medium to store or maintain instructions thatwhen executed by a machine, computing device or system, cause themachine, computing device or system to perform methods and/or operationsin accordance with the described examples. The instructions may includeany suitable type of code, such as source code, compiled code,interpreted code, executable code, static code, dynamic code, and thelike. The instructions may be implemented according to a predefinedcomputer language, manner, or syntax, for instructing a machine,computing device or system to perform a certain function. Theinstructions may be implemented using any suitable high-level,low-level, object-oriented, visual, compiled and/or interpretedprogramming language.

Some examples may be described using the expression “coupled” and“connected” along with their derivatives. These terms are notnecessarily intended as synonyms for each other. For example,descriptions using the terms “connected” and/or “coupled” may indicatethat two or more elements are in direct physical or electrical contactwith each other. The term “coupled,” however, may also mean that two ormore elements are not in direct contact with each other, but yet stillco-operate or interact with each other.

Advantages of Some Embodiments

Several embodiments have one or more potentially advantages effects. Forinstance, use of synchronization logic circuitry, advantageously allowsoperation of time-sensitive applications. With the proposed mechanismwhen 802.11 is the communication medium between two nodes in atime-sensitive network, the corresponding time synchronizationperformance can be estimated on demand by the execution of the ReverseSync procedure (exchange of additional messages between the two nodes)to estimate how tightly the clock at the Follower (the node that gets ittime synchronized to) is synchronized with that of the Leader (the nodethat provides the time value and additional information needed for theFollower to synchronize its local clock). This estimate mayadvantageously be used at the Follower to determine if the timesynchronization meets the requirements of the application(s) supportedover the time-sensitive network; and if not, advantageously triggermitigating mechanisms (e.g., modify the parameters used for executingtime synchronization protocol, explore possibilities of switching tobetter wireless channels, etc.) and restore time synchronizationperformance to acceptable levels.

Examples of Further Embodiments

The following examples pertain to further embodiments. Specifics in theexamples may be used anywhere in one or more embodiments.

Example 1 is an apparatus comprising: a memory; and logic circuitry of aleader device coupled with the memory to: receive a first set of two ormore timing management frames wherein one or more of the two or moretiming management frames in the first set comprise a first adjustedfollower clock value; cause transmission of a second set of two or moretiming management frames, wherein one or more of the two or more timingmanagement frames in the second set comprise a second adjusted clockvalue; cause transmission of a first set of two or more acknowledgementframes; receive a second set of two or more acknowledgement frames; andcalculate a second adjusted clock value; calculate a difference betweenthe first adjusted follower clock value and the second adjusted clockvalue to determine a synchronization error, the synchronization error torepresent a performance of the time synchronization. Example 2 is theapparatus of Example 1, wherein the logic circuitry comprises basebandprocessing circuitry and further comprising a radio coupled with thebaseband processing circuitry, and one or more antennas coupled with theradio to transmit. Example 3 is the apparatus of Example 1, the firstadjusted follower clock value comprising a sum of the local clock at thefollower and the relative offset of the local clock at the follower fromthe local clock of the leader and the second adjusted clock valuecomprising a sum of the local clock at the leader and the relativeoffset of the local clock at the leader from the local clock of thefollower. Example 4 is the apparatus of Example 1, the logic circuitryto further receive a first initial fine timing management frame, causetransmission of a second initial fine timing frame in response toreceipt of the first fine timing management frame, cause transmission ofan acknowledgement in response to receipt of the first fine timingmanagement frame, and receive an acknowledgement in response to thetransmission of a second initial fine timing frame. Example 5 is theapparatus of Example 4, wherein the first fine timing management framecomprises parameters including a number of time management frames in thefirst and second sets of time management frames, a time interval betweentransmission of time management frames in the first and second sets oftime management frames, and a bandwidth of a channel used fortransmission of the first and second sets of time management frames.Example 6 is the apparatus of Example 4, wherein the first set of two ormore timing management frames and the second of two or more timingmanagement frames comprise fine timing management frames. Example 7 isthe apparatus of Example 6, wherein one or more fine timing managementframes of the first set of two or more timing management frames and thesecond of two or more timing management frames comprise a timesynchronization performance information element, the timesynchronization performance information element to comprise a TimeSynchronization Error Threshold field with a value indicative of anupper limit of synchronization error between a time at the Leader and atime at the Follower. Example 8 is the apparatus of Example 1, whereincalculation of the difference comprises calculation in response toreceipt of each acknowledgement in the second set of acknowledgementframes. Example 9 is the apparatus of Example 8, wherein the time framebetween receipt of a time management frame in the first set of timemanagement frames and transmission of a time management frame in thesecond set of time management frames is a minimum of a short interframespace.

Example 10 is a non-transitory computer-readable medium, comprisinginstructions, which when executed by a processor, cause the processor toperform operations to: receive a first set of two or more timingmanagement frames wherein one or more of the two or more timingmanagement frames in the first set comprise a first adjusted followerclock value; cause transmission of a second set of two or more timingmanagement frames, wherein one or more of the two or more timingmanagement frames in the second set comprise a second adjusted clockvalue; cause transmission of a first set of two or more acknowledgementframes; receive a second set of two or more acknowledgement frames; andcalculate a second adjusted clock value; calculate a difference betweenthe first adjusted follower clock value and the second adjusted clockvalue to determine a synchronization error, the synchronization error torepresent a performance of the time synchronization. Example 11 is thenon-transitory computer-readable medium of Example 10, the firstadjusted follower clock value comprising a sum of the local clock at thefollower and the relative offset of the local clock at the follower fromthe local clock of the leader and the second adjusted clock valuecomprising a sum of the local clock at the leader and the relativeoffset of the local clock at the leader from the local clock of thefollower. Example 12 is the non-transitory computer-readable medium ofExample 10, the operations to further receive a first initial finetiming management frame, cause transmission of a second initial finetiming frame in response to receipt of the first fine timing managementframe, cause transmission of an acknowledgement in response to receiptof the first fine timing management frame, and receive anacknowledgement in response to the transmission of a second initial finetiming frame. Example 13 is the non-transitory computer-readable mediumof Example 12, wherein the first fine timing management frame comprisesparameters including a number of time management frames in the first andsecond sets of time management frames, a time interval betweentransmission of time management frames in the first and second sets oftime management frames, and a bandwidth of a channel used fortransmission of the first and second sets of time management frames.Example 14 is the non-transitory computer-readable medium of Example 12,wherein the first set of two or more timing management frames and thesecond of two or more timing management frames comprise fine timingmanagement frames. Example 15 is the non-transitory computer-readablemedium of Example 14, wherein one or more fine timing management framesof the first set of two or more timing management frames and the secondof two or more timing management frames comprise a time synchronizationperformance information element, the time synchronization performanceinformation element to comprise a Time Synchronization Error Thresholdfield with a value indicative of an upper limit of synchronization errorbetween a time at the Leader and a time at the Follower. Example 16 isthe non-transitory computer-readable medium of Example 10, whereincalculation of the difference comprises calculation in response toreceipt of each acknowledgement in the second set of acknowledgementframes. Example 17 is the non-transitory computer-readable medium ofExample 16, wherein the time frame between receipt of a time managementframe in the first set of time management frames and transmission of atime management frame in the second set of time management frames is aminimum of a short interframe space.

Example 18 is a method comprising: receiving a first set of two or moretiming management frames wherein one or more of the two or more timingmanagement frames in the first set comprise a first adjusted followerclock value; causing transmission of a second set of two or more timingmanagement frames, wherein one or more of the two or more timingmanagement frames in the second set comprise a second adjusted clockvalue; transmitting a first set of two or more acknowledgement frames;receiving a second set of two or more acknowledgement frames; andcalculating the second adjusted clock value; calculating a differencebetween the first adjusted follower clock value and the second adjustedclock value to determine a synchronization error, the synchronizationerror to represent a performance of the time synchronization. Example 19is the method of Example 18, the first adjusted follower clock valuecomprising a sum of the local clock at the follower and the relativeoffset of the local clock at the follower from the local clock of theleader and the second adjusted clock value comprising a sum of the localclock at the leader and the relative offset of the local clock at theleader from the local clock of the follower. Example 20 is the method ofExample 18, further comprising receiving a first initial fine timingmanagement frame, causing transmission of a second initial fine timingframe in response to receipt of the first fine timing management frame,causing transmission of an acknowledgement in response to receipt of thefirst fine timing management frame, and receiving an acknowledgement inresponse to the transmission of a second initial fine timing frame.Example 21 is the method of Example 20, wherein the first fine timingmanagement frame comprises parameters including a number of timemanagement frames in the first and second sets of time managementframes, a time interval between transmission of time management framesin the first and second sets of time management frames, and a bandwidthof a channel used for transmission of the first and second sets of timemanagement frames. Example 22 is the method of Example 20, wherein thefirst set of two or more timing management frames and the second of twoor more timing management frames comprise fine timing management frames.Example 23 is the method of Example 22, wherein one or more fine timingmanagement frames of the first set of two or more timing managementframes and the second of two or more timing management frames comprise atime synchronization performance information element, the timesynchronization performance information element to comprise a TimeSynchronization Error Threshold field with a value indicative of anupper limit of synchronization error between a time at the Leader and atime at the Follower. Example 24 is the method of Example 18, whereincalculation of the difference comprises calculation in response toreceipt of each acknowledgement in the second set of acknowledgementframes. Example 25 is the method of Example 24, wherein the time framebetween receipt of a time management frame in the first set of timemanagement frames and transmission of a time management frame in thesecond set of time management frames is a minimum of a short interframespace.

Example 26 is an apparatus comprising: a means for receiving a first setof two or more timing management frames wherein one or more of the twoor more timing management frames in the first set comprise a firstadjusted follower clock value; a means for causing transmission of asecond set of two or more timing management frames, wherein one or moreof the two or more timing management frames in the second set comprise asecond adjusted clock value; a means for transmitting a first set of twoor more acknowledgement frames; a means for receiving a second set oftwo or more acknowledgement frames; and a means for calculating thesecond adjusted clock value; a means for calculating a differencebetween the first adjusted follower clock value and the second adjustedclock value to determine a synchronization error, the synchronizationerror to represent a performance of the time synchronization. Example 27is the apparatus of Example 26, the first adjusted follower clock valuecomprising a sum of the local clock at the follower and the relativeoffset of the local clock at the follower from the local clock of theleader and the second adjusted clock value comprising a sum of the localclock at the leader and the relative offset of the local clock at theleader from the local clock of the follower. Example 28 is the apparatusof Example 26, further comprising receiving a first initial fine timingmanagement frame, causing transmission of a second initial fine timingframe in response to receipt of the first fine timing management frame,causing transmission of an acknowledgement in response to receipt of thefirst fine timing management frame, and receiving an acknowledgement inresponse to the transmission of a second initial fine timing frame.Example 29 is the apparatus of Example 28, wherein the first fine timingmanagement frame comprises parameters including a number of timemanagement frames in the first and second sets of time managementframes, a time interval between transmission of time management framesin the first and second sets of time management frames, and a bandwidthof a channel used for transmission of the first and second sets of timemanagement frames. Example 30 is the apparatus of Example 28, whereinthe first set of two or more timing management frames and the second oftwo or more timing management frames comprise fine timing managementframes. Example 31 is the apparatus of Example 30, wherein one or morefine timing management frames of the first set of two or more timingmanagement frames and the second of two or more timing management framescomprise a time synchronization performance information element, thetime synchronization performance information element to comprise a TimeSynchronization Error Threshold field with a value indicative of anupper limit of synchronization error between a time at the Leader and atime at the Follower. Example 32 is the apparatus of Example 26, whereincalculation of the difference comprises calculation in response toreceipt of each acknowledgement in the second set of acknowledgementframes. Example 33 is the apparatus of Example 32, wherein the timeframe between receipt of a time management frame in the first set oftime management frames and transmission of a time management frame inthe second set of time management frames is a minimum of a shortinterframe space.

Example 34 is an apparatus comprising: a memory; and logic circuitry ofa follower device coupled with the memory to: cause transmission of afirst set of two or more timing management frames wherein one or more ofthe two or more timing management frames in the first set comprise afirst adjusted leader clock value; receive a second set of two or moretiming management frames, wherein one or more of the two or more timingmanagement frames in the second set comprise a second adjusted clockvalue; receive a first set of two or more acknowledgement frames;

calculate the second adjusted clock value; cause transmission of asecond set of two or more acknowledgement frames; and calculate adifference between the first adjusted leader clock value and the secondadjusted clock value to determine a synchronization error, thesynchronization error to represent a performance of the timesynchronization. Example 35 is the apparatus of Example 34, wherein thelogic circuitry comprises baseband processing circuitry and furthercomprising a radio coupled with the baseband processing circuitry, andone or more antennas coupled with the radio to transmit. Example 36 isthe apparatus of Example 34, the first adjusted leader clock valuecomprising a sum of the local clock at the leader and the relativeoffset of the local clock at the leader from the local clock of thefollower and the second adjusted clock value comprising a sum of thelocal clock at the follower and the relative offset of the local clockat the follower from the local clock of the leader. Example 37 is theapparatus of Example 36, the logic circuitry to further receive a firstinitial fine timing management frame, cause transmission of a secondinitial fine timing frame in response to receipt of the first finetiming management frame, cause transmission of an acknowledgement inresponse to receipt of the first fine timing management frame, andreceive an acknowledgement in response to the transmission of a secondinitial fine timing frame. Example 38 is the apparatus of Example 37,wherein the first fine timing management frame comprises parametersincluding a number of time management frames in the first and secondsets of time management frames, a time interval between transmission oftime management frames in the first and second sets of time managementframes, and a bandwidth of a channel used for transmission of the firstand second sets of time management frames. Example 39 is the apparatusof Example 37, wherein the first set of two or more timing managementframes and the second of two or more timing management frames comprisefine timing management frames. Example 40 is the apparatus of Example39, wherein one or more fine timing management frames of the first setof two or more timing management frames and the second of two or moretiming management frames comprise a time synchronization performanceinformation element, the time synchronization performance informationelement to comprise a Time Synchronization Error Threshold field with avalue indicative of an upper limit of synchronization error between atime at the Leader and a time at the Follower. Example 41 is theapparatus of Example 34, wherein calculation of the difference comprisescalculation in response to receipt of each acknowledgement in the secondset of acknowledgement frames. Example 42 is the apparatus of Example34, wherein the time frame between receipt of a time management frame inthe first set of time management frames and transmission of a timemanagement frame in the second set of time management frames is aminimum of a short interframe space.

Example 43 is a non-transitory computer-readable medium, comprisinginstructions, which when executed by a processor, cause the processor toperform operations to: cause transmission of a first set of two or moretiming management frames wherein one or more of the two or more timingmanagement frames in the first set comprise a first adjusted leaderclock value; receive a second set of two or more timing managementframes, wherein one or more of the two or more timing management framesin the second set comprise a second adjusted clock value; receive afirst set of two or more acknowledgement frames; calculate the secondadjusted clock value; cause transmission of a second set of two or moreacknowledgement frames; and calculate a difference between the firstadjusted leader clock value and the second adjusted clock value todetermine a synchronization error, the synchronization error torepresent a performance of the time synchronization. Example 44 is thenon-transitory computer-readable medium of Example 43, the firstadjusted leader clock value comprising a sum of the local clock at theleader and the relative offset of the local clock at the leader from thelocal clock of the follower and the second adjusted clock valuecomprising a sum of the local clock at the follower and the relativeoffset of the local clock at the follower from the local clock of theleader. Example 45 is the non-transitory computer-readable medium ofExample 44, the operations to further receive a first initial finetiming management frame, cause transmission of a second initial finetiming frame in response to receipt of the first fine timing managementframe, cause transmission of an acknowledgement in response to receiptof the first fine timing management frame, and receive anacknowledgement in response to the transmission of a second initial finetiming frame. Example 46 is the non-transitory computer-readable mediumof Example 45, wherein the first fine timing management frame comprisesparameters including a number of time management frames in the first andsecond sets of time management frames, a time interval betweentransmission of time management frames in the first and second sets oftime management frames, and a bandwidth of a channel used fortransmission of the first and second sets of time management frames.Example 47 is the non-transitory computer-readable medium of Example 45,wherein the first set of two or more timing management frames and thesecond of two or more timing management frames comprise fine timingmanagement frames. Example 48 is the non-transitory computer-readablemedium of Example 47, wherein one or more fine timing management framesof the first set of two or more timing management frames and the secondof two or more timing management frames comprise a time synchronizationperformance information element, the time synchronization performanceinformation element to comprise a Time Synchronization Error Thresholdfield with a value indicative of an upper limit of synchronization errorbetween a time at the Leader and a time at the Follower. Example 49 isthe non-transitory computer-readable medium of Example 43, whereincalculation of the difference comprises calculation in response toreceipt of each acknowledgement in the second set of acknowledgementframes. Example 50 is the non-transitory computer-readable medium ofExample 43, wherein the time frame between receipt of a time managementframe in the first set of time management frames and transmission of atime management frame in the second set of time management frames is aminimum of a short interframe space.

Example 50 is a method comprising: causing transmission of a first setof two or more timing management frames wherein one or more of the twoor more timing management frames in the first set comprise a firstadjusted leader clock value; receiving a second set of two or moretiming management frames, wherein one or more of the two or more timingmanagement frames in the second set comprise a second adjusted clockvalue; receiving a first set of two or more acknowledgement frames;calculating the second adjusted clock value; causing transmission of asecond set of two or more acknowledgement frames; and calculating adifference between the first adjusted leader clock value and the secondadjusted clock value to determine a synchronization error, thesynchronization error to represent a performance of the timesynchronization. Example 51 is the method of Example 50, wherein thelogic circuitry comprises baseband processing circuitry and furthercomprising a radio coupled with the baseband processing circuitry, andone or more antennas coupled with the radio to transmit. Example 52 isthe method of Example 50, the first adjusted leader clock valuecomprising a sum of the local clock at the leader and the relativeoffset of the local clock at the leader from the local clock of thefollower and the second adjusted clock value comprising a sum of thelocal clock at the follower and the relative offset of the local clockat the follower from the local clock of the leader. Example 53 is themethod of Example 52, the logic circuitry to further receiving a firstinitial fine timing management frame, causing transmission of a secondinitial fine timing frame in response to receipt of the first finetiming management frame, causing transmission of an acknowledgement inresponse to receipt of the first fine timing management frame, andreceiving an acknowledgement in response to the transmission of a secondinitial fine timing frame. Example 54 is the method of Example 53,wherein the first fine timing management frame comprises parametersincluding a number of time management frames in the first and secondsets of time management frames, a time interval between transmission oftime management frames in the first and second sets of time managementframes, and a bandwidth of a channel used for transmission of the firstand second sets of time management frames. Example 55 is the method ofExample 53, wherein the first set of two or more timing managementframes and the second of two or more timing management frames comprisefine timing management frames. Example 56 is the method of Example 55,wherein one or more fine timing management frames of the first set oftwo or more timing management frames and the second of two or moretiming management frames comprise a time synchronization performanceinformation element, the time synchronization performance informationelement to comprise a Time Synchronization Error Threshold field with avalue indicative of an upper limit of synchronization error between atime at the Leader and a time at the Follower. Example 57 is the methodof Example 50, wherein calculation of the difference comprisescalculation in response to receipt of each acknowledgement in the secondset of acknowledgement frames. Example 58 is the method of Example 50,wherein the time frame between receipt of a time management frame in thefirst set of time management frames and transmission of a timemanagement frame in the second set of time management frames is aminimum of a short interframe space.

Example 59 is an apparatus comprising: a means for causing transmissionof a first set of two or more timing management frames wherein one ormore of the two or more timing management frames in the first setcomprise a first adjusted leader clock value; a means for receiving asecond set of two or more timing management frames, wherein one or moreof the two or more timing management frames in the second set comprise asecond adjusted clock value; a means for receiving a first set of two ormore acknowledgement frames; a means for calculating the second adjustedclock value; a means for causing transmission of a second set of two ormore acknowledgement frames; and a means for calculating a differencebetween the first adjusted leader clock value and the second adjustedclock value to determine a synchronization error, the synchronizationerror to represent a performance of the time synchronization. Example 60is the apparatus of Example 59, wherein the logic circuitry comprisesbaseband processing circuitry and further comprising a radio coupledwith the baseband processing circuitry, and one or more antennas coupledwith the radio to transmit. Example 61 is the apparatus of Example 59,the first adjusted leader clock value comprising a sum of the localclock at the leader and the relative offset of the local clock at theleader from the local clock of the follower and the second adjustedclock value comprising a sum of the local clock at the follower and therelative offset of the local clock at the follower from the local clockof the leader. Example 62 is the apparatus of Example 61, furthercomprising a means for receiving a first initial fine timing managementframe, a means for causing transmission of a second initial fine timingframe in response to receipt of the first fine timing management frame,a means for causing transmission of an acknowledgement in response toreceipt of the first fine timing management frame, and a means forreceiving an acknowledgement in response to the transmission of a secondinitial fine timing frame. Example 63 is the apparatus of Example 62,wherein the first fine timing management frame comprises parametersincluding a number of time management frames in the first and secondsets of time management frames, a time interval between transmission oftime management frames in the first and second sets of time managementframes, and a bandwidth of a channel used for transmission of the firstand second sets of time management frames. Example 64 is the apparatusof Example 62, wherein the first set of two or more timing managementframes and the second of two or more timing management frames comprisefine timing management frames. Example 65 is the apparatus of Example64, wherein one or more fine timing management frames of the first setof two or more timing management frames and the second of two or moretiming management frames comprise a time synchronization performanceinformation element, the time synchronization performance informationelement to comprise a Time Synchronization Error Threshold field with avalue indicative of an upper limit of synchronization error between atime at the Leader and a time at the Follower. Example 66 is theapparatus of Example 59, wherein calculation of the difference comprisescalculation in response to receipt of each acknowledgement in the secondset of acknowledgement frames. Example 67 is the apparatus of Example59, wherein the time frame between receipt of a time management frame inthe first set of time management frames and transmission of a timemanagement frame in the second set of time management frames is aminimum of a short interframe space.

What is claimed is:
 1. An apparatus comprising: a memory; and logiccircuitry of a leader device coupled with the memory to: receive a firstset of two or more timing management frames wherein one or more of thetwo or more timing management frames in the first set comprise a firstadjusted follower clock value; calculate a second adjusted clock value;cause transmission of a second set of two or more timing managementframes, wherein one or more of the two or more timing management framesin the second set comprise the second adjusted clock value; causetransmission of a first set of two or more acknowledgement frames;receive a second set of two or more acknowledgement frames; andcalculate a difference between the first adjusted follower clock valueand the second adjusted clock value to determine a synchronizationerror, the synchronization error to represent a performance of the timesynchronization.
 2. The apparatus of claim 1, wherein the logiccircuitry comprises baseband processing circuitry and further comprisinga radio coupled with the baseband processing circuitry, and one or moreantennas coupled with the radio to transmit.
 3. The apparatus of claim1, the first adjusted follower clock value comprising a sum of the localclock at the follower and the relative offset of the local clock at thefollower from the local clock of the leader and the second adjustedclock value comprising a sum of the local clock at the leader and therelative offset of the local clock at the leader from the local clock ofthe follower.
 4. The apparatus of claim 1, the logic circuitry tofurther receive a first initial fine timing management frame, causetransmission of a second initial fine timing frame in response toreceipt of the first fine timing management frame, cause transmission ofan acknowledgement in response to receipt of the first fine timingmanagement frame, and receive an acknowledgement in response to thetransmission of a second initial fine timing frame.
 5. The apparatus ofclaim 4, wherein the first fine timing management frame comprisesparameters including a number of time management frames in the first andsecond sets of time management frames, a time interval betweentransmission of time management frames in the first and second sets oftime management frames, and a bandwidth of a channel used fortransmission of the first and second sets of time management frames. 6.The apparatus of claim 4, wherein the first set of two or more timingmanagement frames and the second of two or more timing management framescomprise fine timing management frames.
 7. The apparatus of claim 6,wherein one or more fine timing management frames of the first set oftwo or more timing management frames and the second of two or moretiming management frames comprise a time synchronization performanceinformation element, the time synchronization performance informationelement to comprise a Time Synchronization Error Threshold field with avalue indicative of an upper limit of synchronization error between atime at the Leader and a time at the Follower.
 8. The apparatus of claim1, wherein calculation of the difference comprises calculation inresponse to receipt of each acknowledgement in the second set ofacknowledgement frames.
 9. The apparatus of claim 8, wherein the timeframe between receipt of a time management frame in the first set oftime management frames and transmission of a time management frame inthe second set of time management frames is a minimum of a shortinterframe space.
 10. A non-transitory computer-readable medium,comprising instructions, which when executed by a processor, cause theprocessor to perform operations to: receive a first set of two or moretiming management frames wherein one or more of the two or more timingmanagement frames in the first set comprise a first adjusted followerclock value; calculate a second adjusted clock value; cause transmissionof a second set of two or more timing management frames, wherein one ormore of the two or more timing management frames in the second setcomprise the second adjusted clock value; cause transmission of a firstset of two or more acknowledgement frames; receive a second set of twoor more acknowledgement frames; and calculate a difference between thefirst adjusted follower clock value and the second adjusted clock valueto determine a synchronization error, the synchronization error torepresent a performance of the time synchronization.
 11. Thenon-transitory computer-readable medium of claim 10, the first adjustedfollower clock value comprising a sum of the local clock at the followerand the relative offset of the local clock at the follower from thelocal clock of the leader and the second adjusted clock value comprisinga sum of the local clock at the leader and the relative offset of thelocal clock at the leader from the local clock of the follower.
 12. Thenon-transitory computer-readable medium of claim 10, the operations tofurther receive a first initial fine timing management frame, causetransmission of a second initial fine timing frame in response toreceipt of the first fine timing management frame, cause transmission ofan acknowledgement in response to receipt of the first fine timingmanagement frame, and receive an acknowledgement in response to thetransmission of a second initial fine timing frame.
 13. Thenon-transitory computer-readable medium of claim 12, wherein the firstfine timing management frame comprises parameters including a number oftime management frames in the first and second sets of time managementframes, a time interval between transmission of time management framesin the first and second sets of time management frames, and a bandwidthof a channel used for transmission of the first and second sets of timemanagement frames.
 14. An apparatus comprising: a memory; and logiccircuitry of a follower device coupled with the memory to: receive afirst set of two or more timing management frames wherein one or more ofthe two or more timing management frames in the first set comprise afirst adjusted leader clock value; calculate a second adjusted clockvalue; cause transmission of a second set of two or more timingmanagement frames, wherein one or more of the two or more timingmanagement frames in the second set comprise the second adjusted clockvalue; cause transmission of a first set of two or more acknowledgementframes; receive a second set of two or more acknowledgement frames; andcalculate a difference between the first adjusted leader clock value andthe second adjusted clock value to determine a synchronization error,the synchronization error to represent a performance of the timesynchronization.
 15. The apparatus of claim 14, wherein the logiccircuitry comprises baseband processing circuitry and further comprisinga radio coupled with the baseband processing circuitry, and one or moreantennas coupled with the radio to transmit.
 16. The apparatus of claim14, the first adjusted leader clock value comprising a sum of the localclock at the leader and the relative offset of the local clock at theleader from the local clock of the follower and the second adjustedclock value comprising a sum of the local clock at the follower and therelative offset of the local clock at the follower from the local clockof the leader.
 17. The apparatus of claim 16, the logic circuitry tofurther receive a first initial fine timing management frame, causetransmission of a second initial fine timing frame in response toreceipt of the first fine timing management frame, cause transmission ofan acknowledgement in response to receipt of the first fine timingmanagement frame, and receive an acknowledgement in response to thetransmission of a second initial fine timing frame.
 18. The apparatus ofclaim 17, wherein the first fine timing management frame comprisesparameters including a number of time management frames in the first andsecond sets of time management frames, a time interval betweentransmission of time management frames in the first and second sets oftime management frames, and a bandwidth of a channel used fortransmission of the first and second sets of time management frames. 19.The apparatus of claim 17, wherein the first set of two or more timingmanagement frames and the second of two or more timing management framescomprise fine timing management frames.
 20. The apparatus of claim 19,wherein one or more fine timing management frames of the first set oftwo or more timing management frames and the second of two or moretiming management frames comprise a time synchronization performanceinformation element, the time synchronization performance informationelement to comprise a Time Synchronization Error Threshold field with avalue indicative of an upper limit of synchronization error between atime at the Leader and a time at the Follower.
 21. The apparatus ofclaim 14, wherein calculation of the difference comprises calculation inresponse to receipt of each acknowledgement in the second set ofacknowledgement frames.
 22. The apparatus of claim 14, wherein the timeframe between receipt of a time management frame in the first set oftime management frames and transmission of a time management frame inthe second set of time management frames is a minimum of a shortinterframe space.
 23. A non-transitory computer-readable medium,comprising instructions, which when executed by a processor, cause theprocessor to perform operations to: receive a first set of two or moretiming management frames wherein one or more of the two or more timingmanagement frames in the first set comprise a first adjusted leaderclock value; calculate a second adjusted clock value; cause transmissionof a second set of two or more timing management frames, wherein one ormore of the two or more timing management frames in the second setcomprise the second adjusted clock value; cause transmission of a firstset of two or more acknowledgement frames; receive a second set of twoor more acknowledgement frames; and calculate a difference between thefirst adjusted leader clock value and the second adjusted clock value todetermine a synchronization error, the synchronization error torepresent a performance of the time synchronization.
 24. Thenon-transitory computer-readable medium of claim 23, the first adjustedleader clock value comprising a sum of the local clock at the leader andthe relative offset of the local clock at the leader from the localclock of the follower and the second adjusted clock value comprising asum of the local clock at the follower and the relative offset of thelocal clock at the follower from the local clock of the leader.
 25. Thenon-transitory computer-readable medium of claim 24, the operations tofurther receive a first initial fine timing management frame, causetransmission of a second initial fine timing frame in response toreceipt of the first fine timing management frame, cause transmission ofan acknowledgement in response to receipt of the first fine timingmanagement frame, and receive an acknowledgement in response to thetransmission of a second initial fine timing frame.